pi7c8154a Pericom Semiconductor Corporation, pi7c8154a Datasheet - Page 8

• Manufacturer Part Number: pi7c8154a
• Description: 2-port Pci-to-pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

15
16
15.1
15.2
16.1
14.1.27
14.1.28
14.1.29
14.1.30
14.1.31
14.1.32
14.1.33
14.1.34
14.1.35
14.1.36
14.1.37
14.1.38
14.1.39
14.1.40
14.1.41
5Ch
14.1.42
60h
14.1.43
14.1.44
14.1.45
14.1.46
14.1.47
14.1.48
14.1.49
14.1.50
14.1.51
14.1.52
14.1.53
14.1.54
14.1.55
14.1.56
14.1.57
14.1.58
14.1.59
14.1.60
14.1.61
14.1.62
14.1.63
14.1.64
14.1.65
14.1.66
BRIDGE BEHAVIOR .............................................................................................................................100
15.2.1
15.2.2
15.2.3
15.2.4
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER .........................................................................101
16.1.1
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES....................................................................100
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) .........................................100
BOUNDARY SCAN ARCHITECTURE .........................................................................................101
INTERRUPT LINE REGISTER – OFFSET 3Ch .......................................................................84
INTERRUPT PIN REGISTER – OFFSET 3Ch .........................................................................84
BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................................84
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h................................................86
ARBITER CONTROL REGISTER – OFFSET 40h....................................................................86
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h.....................................................87
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h..............................................88
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch..........88
HOT SWAP SWITCH TIME SLOT REGISTER – OFFSET 4Ch...............................................88
EEPROM AUTOLOAD CONTROL / STATUS REGISTER – OFFSET 50h .............................89
EEPROM ADDRESS / CONTROL REGISTER – OFFSET 54h ...............................................89
EEPROM DATA REGISTER – OFFSET 54h ...........................................................................89
UPSTREAM (S TO P) MEMORY BASE ADDRESS REGISTER – OFFSET 58h .....................90
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS REGISTER – OFFSET 58h ....................90
UPSTREAM (S TO P) MEMORY BASE ADDRESS UPPER 32-BIT REGISTER – OFFSET
90
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS UPPER 32-BIT REGISTER – OFFSET
90
P_SERR# EVENT DISABLE REGISTER – OFFSET 64h.........................................................90
GPIO DATA AND CONTROL REGISTER – OFFSET 64h ......................................................92
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h...............................................92
P_SERR# STATUS REGISTER – OFFSET 68h........................................................................94
PORT OPTION REGISTER – OFFSET 74h .............................................................................94
SECONDARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h...........................96
PRIMARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h.................................96
CAPABILITY ID REGISTER – OFFSET B0h ...........................................................................96
NEXT POINTER REGISTER – OFFSET B0h...........................................................................96
SLOT NUMBER REGISTER – OFFSET B0h ...........................................................................96
CHASSIS NUMBER REGISTER – OFFSET B0h .....................................................................97
CAPABILITY ID REGISTER – OFFSET DCh..........................................................................97
NEXT ITEM POINTER REGISTER – OFFSET DCh ...............................................................97
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh .................................97
POWER MANAGEMENT DATA REGISTER – OFFSET E0h..................................................97
PPB SUPPORT EXTENSIONS REGISTER – OFFSET E0h ....................................................98
DATA REGISTER – OFFSET E0h............................................................................................98
CAPABILITY ID REGISTER – OFFSET E4h ...........................................................................98
NEXT POINTER REGISTER – OFFSET E4h...........................................................................98
HOT SWAP CONTROL AND STATUS REGISTER – OFFSET E4h ........................................98
CAPABILITY ID REGISTER – OFFSET E8h ...........................................................................99
NEXT POINTER REGISTER – OFFSET E8h...........................................................................99
VPD REGISTER – OFFSET E8h ..............................................................................................99
VPD DATA REGISTER – OFFSET ECh ..................................................................................99
MASTER ABORT ....................................................................................................................100
PARITY AND ERROR REPORTING ......................................................................................100
REPORTING PARITY ERRORS .............................................................................................101
SECONDARY IDSEL MAPPING............................................................................................101
TAP PINS ................................................................................................................................102
Page 8 of 112
ASYNCHRONOUS 2-PORT
JULY 2004 REVISION 1.00
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A