pi7c8154a Pericom Semiconductor Corporation, pi7c8154a Datasheet - Page 80
pi7c8154a
Manufacturer Part Number
pi7c8154a
Description
2-port Pci-to-pci Bridge
Manufacturer
Pericom Semiconductor Corporation
Datasheet
1.PI7C8154A.pdf
(112 pages)
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14.1.10
14.1.11
14.1.12
14.1.13
14.1.14
14.1.15
HEADER TYPE REGISTER – OFFSET 0Ch
PRIMARY BUS NUMBER REGISTER – OFFSET 18h
SECONDARY BUS NUMBER REGISTER – OFFSET 18h
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h
SECONDARY LATENCY TIMER – OFFSET 18h
I/O BASE REGISTER – OFFSET 1Ch
Bit
23:16
Bit
7:0
Bit
15:8
Bit
23:16
Bit
31:24
Bit
1:0
3:2
Function
Header Type
Function
Primary Bus
Number
Function
Secondary Bus
Number
Function
Subordinate Bus
Number
Function
Secondary
Latency Timer
Function
32-bit Indicator
Reserved
Type
R/O
Type
R/W
Type
R/W
Type
R/W
Type
R/W
Type
R/O
R/O
Page 80 of 112
Description
Read as 01h to indicate that the register layout conforms to the standard
PCI-to-PCI bridge layout.
Description
Indicates the number of the PCI bus to which the primary interface is
connected. The value is set in software during configuration.
Reset to 0
Description
Indicates the number of the PCI bus to which the secondary interface is
connected. The value is set in software during configuration.
Reset to 0
Description
Indicates the number of the PCI bus with the highest number that is
subordinate to the bridge. The value is set in software during
configuration.
Reset to 0
Description
Designated in units of PCI bus clocks. Latency timer checks for master
accesses on the secondary bus interfaces that remain unclaimed by any
target.
Reset to 0
Description
Read as 01h to indicate 32-bit I/O addressing
Returns 00 when read. Reset to 00.
ASYNCHRONOUS 2-PORT
JULY 2004 REVISION 1.00
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A
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