pi7c8154a Pericom Semiconductor Corporation, pi7c8154a Datasheet - Page 39

• Manufacturer Part Number: pi7c8154a
• Description: 2-port Pci-to-pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

2.11.3
2.11.3.1
PI7C8154A asserts P_SERR# if the master-abort-on-posted-write is not set. The master-abort-on-
posted-write bit is bit 4 of the P_SERR# event disable register (offset 64h).
Note: When PI7C8154A performs a Type 1 to special cycle conversion, a master abort is the
expected termination for the special cycle on the target bus. In this case, the master abort received
bit is not set, and the Type 1 configuration transaction is disconnected after the first data phase.
TARGET TERMINATION RECEIVED BY PI7C8154A
When PI7C8154A initiates a transaction on the target bus and the target responds with DEVSEL#,
the target can end the transaction with one of the following types
of termination:
!
!
!
!
PI7C8154A handles these terminations in different ways, depending on the type of transaction
being performed.
DELAYED WRITE TARGET TERMINATION RESPONSE
When PI7C8154A initiates a delayed write transaction, the type of target termination received from
the target can be passed back to the initiator.
Normal termination (upon de-assertion of FRAME#)
Target retry
Target disconnect
Target abort
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ASYNCHRONOUS 2-PORT
JULY 2004 REVISION 1.00
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A