pca2125 NXP Semiconductors, pca2125 Datasheet - Page 18

• Manufacturer Part Number: pca2125
• Description: Spi Real Time Clock / Calendar Semiconductors
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA2125_00
Preliminary data sheet
6.6.3 Timer flags
countdown counter which results an undetermined countdown period for the first period.
The countdown value n will however be correctly stored and correctly loaded on
subsequent timer periods.
When the countdown timer flag is set, an interrupt signal on INT will be generated
provided that this mode is enabled. See
be controlled.
When starting the timer for the first time, the first period will have an uncertainty which is a
result of the enable instruction being generated from the interface clock which is
asynchronous from the timer source clock. Subsequent timer periods will have no such
delay. The amount of delay for the first timer period will depend on the chosen source
clock, see
Table 31:
At the end of every countdown, the timer sets the countdown Timer Flag (TF). The TF may
only be cleared by software. The asserted TF can be used to generate an interrupt (INT).
The interrupt may be generated as a pulsed signal every countdown period or as a
permanently active signal which follows the condition of TF. Bit TI/TP is used to control
this mode selection and the interrupt output may be disabled with the TIE bit, see
Table
When reading the timer, the current countdown value is returned and not the initial value,
n. For accurate read back of the countdown value, the SPI bus clock (SCL) must be
operating at a frequency of at least twice the selected timer clock. Since it is not possible
to freeze the countdown timer counter during read back, it is recommended to read the
register twice and check for consistent results.
When a minute or second interrupt occurs, MSF is set to 1. Similarly, at the end of a timer
countdown, TF is set to 1. These bits maintain their value until overwritten by software. If
both countdown timer and minute/second interrupts are required in the application, the
source of the interrupt can be determined by reading these bits. To prevent one flag being
overwritten while clearing another a logic AND is performed during a write access. Writing
a ‘1’ will cause the flag to maintain it’s value, whilst writing a ‘0’ will cause the flag to be
reset.
Three examples are given for clearing the flags. Clearing the flags is made by a write
command, therefore bits 7,6,4,1 and 0 must be written with their previous values.
Repeatedly re-writing these bits has no influence on the functional behavior.
Table 32:
Timer source clock
4096 Hz
64 Hz
1 Hz
1/60 Hz
Register
Control 2
25.
Table
First period delay for timer counter value, n.
Flag location in control 2
Bit 7
-
31.
Rev. 00.11 — 30 January 2007
Bit 6
-
minimum timer period
n
n
(n-1) + 1/64Hz
(n-1) + 1/64Hz
Bit 5
MSF
Section 6.7.2
Bit 4
-
Bit 3
AF
for details on how the interrupt can
SPI Real time clock / calendar
maximum timer period
n + 1
n + 1
n + 1/64Hz
n + 1/64Hz
Bit 2
TF
PCA2125
© NXP B.V. 2007. All rights reserved.
Bit 1
-
Bit 0
-
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