adf4001 Analog Devices, Inc., adf4001 Datasheet - Page 6

• Manufacturer Part Number: adf4001
• Description: 200 Mhz Clock Generator Pll
• Manufacturer: Analog Devices, Inc.

ADF4001
CIRCUIT DESCRIPTION
Reference Input Section
The reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
RF Input Stage
The RF input stage is shown in Figure 3. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the N counter buffer.
N Counter
The N CMOS counter allows a wide ranging division ratio
in the PLL feedback counter. Division ratios of 1 to 8191
are allowed.
N and R Relationship
The N counter with the R counter make it possible to generate
output frequencies that are spaced only by the reference fre-
quency divided by R. The equation for the VCO frequency is
f
oscillator (VCO).
N is the preset divide ratio of the binary 13-bit counter
(1 to 8,191).
f
R is the preset divide ratio of the binary 14-bit programmable
reference counter (1 to 16,383).
VCO
REFIN
is the output frequency of the external voltage cotrolled
is the external reference frequency oscillator.
RF
RF
IN
IN
REF
A
B
IN
Figure 2. Reference Input Stage
NC
Figure 3. RF Input Stage
GENERATOR
SW1
POWER-DOWN
f
VCO
CONTROL
BIAS
=
NO
N R
NC
2k
SW3
SW2
×
1.6V
100k
f
REFIN
2k
BUFFER
AGND
AV
DD
TO
R COUNTER
IN
pin
–6–
R Counter
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic.
The PFD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that no
dead zone is in the PFD transfer function and minimizes phase
noise and reference spurs. Two bits in the reference counter
latch, ABP2 and ABP1, control the width of the pulse (see
Table III).
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4001 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Table V shows the full truth table. Figure 6 shows the
MUXOUT section in block diagram form.
CP OUTPUT
N DIVIDER
Figure 5. PFD Simplified Schematic and Timing (In Lock)
R DIVIDER
R DIVIDER
N DIVIDER
INPUT STAGE
FROM RF
HI
HI
D2
D1
CLR2
CLR1
Figure 4. N Counter
U1
U2
Q2
Q1
DELAY
UP
DOWN
N COUNTER LATCH
COUNTER
13-BIT N
FROM
U3
CPGND
TO PFD
V
P
CHARGE
PUMP
REV. A
CP