ad8366 Analog Devices, Inc., ad8366 Datasheet
ad8366
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ad8366 Summary of contents
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... OFSB. The input common mode also defaults driven from 1.2V to 3.4V. The digital interface allows for parallel or serial gain programming. The AD8366 operates off a 4.5V to 5.5V supply and consumes a supply current of 175mA. When disabled, it consumes ~ 4mA. The AD8366 is fabricated using Analog Devices’ advanced Silicon-Germanium bipolar process and is available in a 32-lead exposed paddle LFCSP package ...
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... AD8366 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 REVISION HISTORY 10/07—Revision PrA: Initial Version 02/08—Revision PrB: Updated Performance Specifications 06/08—Revision PrC: Evaluation Board Section Preliminary Technical Data ESD Caution...................................................................................5 Pin Configuration and Function Descriptions..............................6 Typical Performance Characteristics ...
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... V p-p composite, Min. Gain, ZL= 200Ώ Max. gain, ZL=500Ώ Min. Gain, ZL=500Ώ Max Gain Min Gain 2 Vp-p output , Max Gain Min Gain 2 V p-p output, Max Gain Min Gain Rev. PrC | Page AD8366 Min Typ Max Unit MHz 1000 250 MHz TBD ...
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... AD8366 OIP3 Output 1 dB Compression Point 100 MHz Noise Figure nd 2 Harmonic rd 3 Harmonic OIP3 Output 1 dB Compression Point DIGITAL LOGIC V , Input High Voltage INH V , Input Low Voltage INL Input Current INH INL C , Input Capacitance IN SPI INTERFACE TIMING f SCLK ...
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... Exposure to absolute maximum rating conditions for extended periods may affect TBD V device reliability. TBD V TBD V TBD V ESD CAUTION TBD mW TBD°C/W 125°C −40°C to +85°C −65°C to +150°C 300°C Rev. PrC | Page AD8366 ...
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... OPPB, OPMB, OPMA, OPPA 16, 17 DENB, DENA 18, 19, 21, 22, 23, 24 BIT5, BIT4, BIT3, BIT2, BIT1, BIT0 25 SENB AD8366 4 TOP VIEW Figure 2. Pin Configuration Description Input and Output Stage Positive Supply Voltage. 4.5 V − 5.5 V. Differential Inputs Chip Enable. Pull high to enable. ...
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... Rev. PrC | Page 50MHz 10MHz Gaincodes Ideal Gain (dB) Figure 7. IQ Phase Mismatch at 10 MHz vs. Ideal Gain -19.00 -17.00 -15.00 -13.00 -11.00 -9.00 -7.00 Input (dBV ) RMS 10MHz AD8366 100MHz 22.00 21.00 20.00 19.00 18.00 17.00 16.00 15.00 14.00 13.00 12.00 11.00 10.00 -5.00 -3.00 -1.00 ...
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... AD8366 APPLICATIONS SCHEMATIC VPOS 0Ω VPOS 0.01µF 10kΩ 0.1µF 0Ω VPOS C 1000pF OFS 0.01µF VPSIA IPPA IPMA AD8366 VPOS ENBL ICOM IPMB IPPB VPSIB 0Ω VPOS C 1000pF OFS 0.01µF 10kΩ 0.01µF 0Ω VPOS Figure 9 Applications Schematic with Basic Connections Rev ...
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... Preliminary Technical Data EVALUATION BOARD Figure 10. Evaluation Board Schematic Rev. PrC | Page AD8366 ...
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... S1, S5, S7, R53, R57, R79, Enable Interface. C29, C30, C31 -Device Enable. The AD8366 is enabled by applying a logic high voltage to the ENBL pin. The device is enabled when the switch S1 is set in the down position (HIGH), connecting the ENBL pin to VPOS. -Data Enable. DENA and DENB are used to enable the data path for Channel A and Channel B respectively ...
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... Vpos/2 Reference Output Decoupling Capacitor to circuit common. C4, C17 Output Common-mode Centering Loop Compensation. Connect capacitor to circuit common Rev. PrC | Page AD8366 R10, R24= 10 kΩ Potentiometers R22, R28= 0Ω C2, C3= 0.1μF (size 0402) C11, C12= 0.01μF (size 0402) C4, C17 (size 0402) ...
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... AD8366 PARALLEL AND SERIAL INTERFACE TIMING SCLK 0 1 B-LSB SDATA 0 LOAD DATA INTO SERIAL REGISTER ON RISING EDGE. 1 SENB 0 1 BIT[0-6] X GAIN DENA DENB 0 1 SENB 0 PROGRAM A ONLY B-MSB A-LSB Figure 11. SPI Port Timing Diagram ...
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... BSC 4.75 BSC SQ 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 COPLANARITY 0.20 REF 0.23 0.08 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 13. Outline Dimensions. Package Description Evaluation Board Rev. PrC | Page 0.60 MAX PIN 1 INDICATOR EXPOSED 3.65 PAD 3.50 SQ (BOTTOM VIEW) 3. 0.25 MIN 3.50 REF Package Option PR07584-0-6/08(PrC) AD8366 ...