ad8366 Analog Devices, Inc., ad8366 Datasheet - Page 10

• Manufacturer Part Number: ad8366
• Description: Dc To 500 Mhz, Dual Digital Gain Trim Amplifier
• Manufacturer: Analog Devices, Inc.

AD8366
Table 4. Evaluation Board Configuration Options
Components
C1, C13 to C16, R3 to R6
T1, T2, C5,C18,C20,C21,
R12 to R21, R44 to R48,
R50, R54, R58, R62, R63
T3, T4, C24 to C27,
R29 to R31,R33 to
R39,R65,R67 to R74, R80
S1, S5, S7, R53, R57, R79,
C29, C30, C31
S2,S3,S4,S6,S8,S9, S10
R26, R32, R40-R43,
R61,R64
C23, C33
U1
S11, S12, C9, C10
Function
Power Supply Decoupling. Nominal supply decoupling consists a
0.1μF capacitor to ground followed by 0.01 μF capacitors to ground
positioned as close to the device as possible.
Input Interface. The default configuration of the Eval board is for
single ended operation. T1 and T2 are 4:1 impedance ratio baluns to
transform a 50 Ω single-ended input into a 200 Ω-balanced
differential signal. R12 to R14 and R15, R16, and R19 are populated
for appropriate balun interface. R44 to R48 and R50, R54, R58, R62,
andR63 are provided for generic placement of matching
components. C5 to C20 are balun decoupling capacitors.
R17, R18, R20, R21 can be populated with 0 Ω and the balun
interfacing resistors can be removed to bypass T1 and T2 for
differential interfacing.
Output Interface. The default configuration of the Eval board is for
single ended operation. T3 and T4 are 4:1 impedance ratio baluns to
transform a 50 Ω single-ended output into a 200 Ω-balanced
differential load. R29 to R31, R33, R38, R39 are populated for
appropriate balun interface. R65, R67 to R74, and R80 are provided
for generic placement of matching components. C24, C25 are balun
decoupling capacitors.
R34 to R37 can be populated with 0 Ω and the balun interfacing
resistors can be removed to bypass T3 and T4 for differential
interfacing.
Enable Interface.
voltage to the ENBL pin. The device is enabled when the switch S1 is
set in the down position (HIGH), connecting the ENBL pin to VPOS.
-Data Enable. DENA and DENB are used to enable the data path for
Channel A and Channel B respectively. Channel A is enabled when
the switch S5 is set in the down position (HIGH), connecting the
DENA pin to VPOS. Likewise, Channel B is enabled when the switch
S7 is set in the down position (HIGH), connecting the DENB pin to
VPOS. Both channels are disabled by setting the switches to the up
position, connecting the DENA and DENB pins to GND.
Serial/Parallel Interface Control. SENB is used to set the data
control either in parallel or serial mode. Parallel Interface is enabled
when the switch S4 is up position (LOW). Serial interface enabled
when S4 is in the down position (HIGH).
For SENB pulled LOW,
For SENB pulled HIGH, BIT0 becomes a chip-select (CS), BIT1
becomes serial data input, SDAT, and BIT2 becomes serial clock,
SCLK. BIT3-BIT5 are not used in the serial mode.
DC Offset Correction Loop Compensation. The DC offset
correction loop is enabled (HIGH) with switch S11 and S12 for
channel A and channel B respectively. When enabled, the capacitor
is connected to circuit common. When disabled (LOW), the
OFSA/OFSB pins are tied to common.
-Device Enable. The AD8366 is enabled by applying a logic high
BIT0 (switch S9) sets 0.25dB Gain
BIT1 (switch S2) sets 0.5dB Gain
BIT2 (switch S3) sets 1dB Gain
BIT3 (switch S6)sets 2dB Gain
BIT4 (switch S8)sets 4dB Gain
BIT5 (switch S10) sets 8dB Gain
Rev. PrC | Page 10 of 13
Preliminary Technical Data
Default Conditions
C1 = 0.1μF (size 0603)
C13 to C16 = 0.01 μF (size 0402)
R3 to R6 = 0 Ω (size 0603)
T1, T2 = ADT4-6T+ (Mini-Circuits)
C5,C20 = 0.1 μF (size 0402)
C18,C21 = Do not install
R12 to R16, R19, R44 to R47= 0 Ω (size
0402)
R17, R18, R20, R21,R48, R50, R54, R58,
R62, andR63 = open (size 0402)
T3, T4 = ADT4-6T+ (Mini-Circuits)
C24,C25 = 0.1 μF (size 0402)
C26,C27 = Do not install
R29 to R31, R33, R38, R39, R65, R67,
R68, R80 = 0 Ω (size 0402)
R34 to R37, R69 to R74= open (size
0402)
S1,S5,S7 = installed
R53, R57= 5.1kΩ (size 0603)
R79 = 10kΩ (size 0402)
C30=0.01uF (size 0402)
C29, C31=1500pF (size 0402)
S2,S3,S4, S6, S8, S9, 10 = installed
R26=698 kΩ (size 0603)
R32, R40-R43, R61,R64 = 5.1kΩ (size
0603)
C23, C33 = 1500pF (size 0603)
U1= SN74LVC2G14, Clock Chip
S11, S12 = installed
C9, C10=8200pF (size 0402)