ad8366 Analog Devices, Inc., ad8366 Datasheet - Page 4

• Manufacturer Part Number: ad8366
• Description: Dc To 500 Mhz, Dual Digital Gain Trim Amplifier
• Manufacturer: Analog Devices, Inc.

AD8366
100 MHz
DIGITAL LOGIC
SPI INTERFACE TIMING
PARALLEL PORT TIMING
POWER AND ENABLE
V
V
I
C
f
t
t
t
t
t
t
t
t
t
t
Supply Voltage Range
Total Supply Current
Disable Current
Disable Threshold
Enable Response Time
Disable Response Time
INH
SCLK
1
2
3
4
5
6
7
8
9
10
INH
INL
IN
OIP3
Output 1 dB Compression Point
Noise Figure
2
3
OIP3
Output 1 dB Compression Point
, Input Capacitance
/I
, Input Low Voltage
, Input High Voltage
nd
rd
INL
Harmonic
Harmonic
, Input Current
SENB = HIGH
SENB = LOW
VPSI, VPSO, ICOM, OCOM, ENBL
2 V p-p composite, Max. Gain, ZL=500Ώ
2 V p-p composite, Min. Gain, ZL=500Ώ
Max. gain, ZL=500Ώ
Min. Gain, ZL=500Ώ
Max Gain
Min Gain
2 Vp-p output , Max Gain
Min Gain
2 Vp-p output, Max Gain
Min Gain
2Vp-p composite, Max. Gain @ 500 Load impedance
Min. Gain
Max. gain
Min. Gain
SENB, DENA, DENB, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5
CS rising edge to first SCLK rising edge
SCLK high pulse width
SCLK low pulse width
SDAT setup time
SDAT hold time
SCLK falling edge to CS low
DENA/B high pulse width
DENA/B low pulse width
BIT[0-5] setup time
BIT[0-5] hold time
ENBL = 5V
ENBL = 0V
Delay following high-to-low transition until device
meets full specifications
Delay following low-to-high transition until device
produces full attenuation
Rev. PrC | Page 4 of 13
Preliminary Technical Data
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
4.5
34.2
30.7
7.2
11.84
18.8
TBD
TBD
TBD
TBD
29.5
21
4
6
180
3.2
TBD
TBD
TBD
6.7
TBD
TBD
TBD
TBD
5.5
dBVrms
dBVrms
dBVrms
dBVrms
dB
dB
dBc
dBc
dBc
dBc
dBVrms
dBVrms
dBVrms
dBVrms
V
V
μA
pF
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
mA
mA
V
ns
ns