pcf2113du/f4 NXP Semiconductors, pcf2113du/f4 Datasheet - Page 56

• Manufacturer Part Number: pcf2113du/f4
• Description: Pcf2113x Lcd Controllers/drivers
• Manufacturer: NXP Semiconductors

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12 to 15
STEP
16
17
18
19
20
21
22
23
24
‘write data’ to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
(optional I
address for write (as step 8)
control byte
Co
1
return home
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
I
slave address for read
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
0
control byte for read
Co
0
‘read data’: 8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
X
‘read data’: 8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
2
C-bus start
1
RS
0
0
1
RS
1
X
1
2
C-bus stop) I
0
0
0
0
1
0
1
X
0
SCL + master acknowledge; note 2
SCL + master acknowledge; note 2
1
0
0
0
1
0
0
X
0
I
2
C-BUS BYTE
2
C-bus start start + slave
0
0
0
0
0
0
0
X
1
|
|
0
0
0
0
1
0
0
X
0
1
0
0
1
0
0
0
X
0
1
0
0
0
1
0
0
X
0
1
Ack
1
1
1
Ack
1
0
0
PHILIPS_
PHILIPS_
PHILIPS_
PHILIPS
PHILIPS
PHILIPS
PHILIPS
PHILIPS
PHILIPS
DISPLAY
writes ‘S’
sets DDRAM address 0 in address counter (also returns shifted
display to original position; DDRAM contents unchanged); this
instruction does not update the Data Register (DR)
during the acknowledge cycle the content of the DR is loaded
into the internal I
previous instruction neither a ‘set address’ nor a ‘read data’ has
been performed; therefore the content of the DR was unknown;
the R/W has to be set to 1 while still in I
DDRAM content will be read from following instructions
8
acknowledge cycle is shifted out over SDA; MSB is DB7; during
master acknowledge content of DDRAM address 01 is loaded
into the I
8
acknowledge code of ‘I’ is loaded into the I
SCL; content loaded into interface during previous
SCL; code of letter ‘H’ is read first; during master
2
C-bus interface
2
C-bus interface to be shifted out; in the
OPERATION
2
C-write mode
2
C-bus interface