pcf8563 NXP Semiconductors, pcf8563 Datasheet - Page 12

• Manufacturer Part Number: pcf8563
• Description: Real-time Clock/calendar
• Manufacturer: NXP Semiconductors

NXP Semiconductors
8. Characteristics of the I
PCF8563_5
Product data sheet
Fig 8. POR override sequence
SDA
SCL
power up
8 ms
Once the override mode has been entered, the device immediately stops being reset and
normal operation may commence i.e. entry into the EXT_CLK test mode via I
access. The override mode may be cleared by writing a logic 0 to TESTC. TESTC must be
set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0
during normal operation has no effect except to prevent entry into the POR override mode.
Table 25
Table 25:
[1]
The I
The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
Address Register name
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
registers marked ‘x’ are undefined at power-up and unchanged by subsequent resets.
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
shows the register reset values.
control/status 1
control/status 2
seconds
minutes
hours
days
weekdays
months/century
years
minute alarm
hour alarm
day alarm
weekday alarm
CLKOUT control
timer control
timer
500 ns
Register reset value
2
C-bus
Rev. 05 — 17 July 2007
2000 ns
[1]
Bit 7
0
x
1
1
x
x
x
x
x
1
1
1
1
1
0
x
Bit 6
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Bit 5
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Bit 4
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
override active
Bit 3
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Real time clock/calendar
Bit 2
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PCF8563
© NXP B.V. 2007. All rights reserved.
mgm664
Bit 1
2
0
0
x
x
x
x
x
x
x
x
x
x
x
0
1
x
C-bus
12 of 32
Bit 0
0
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x