pcf8563 NXP Semiconductors, pcf8563 Datasheet - Page 5

• Manufacturer Part Number: pcf8563
• Description: Real-time Clock/calendar
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8563_5
Product data sheet
7.2 Timer
7.3 Clock output
7.4 Reset
7.5 Voltage-low detector
The 8-bit countdown timer at address 0Fh is controlled by the timer control register at
address 0Eh. The timer control register determines one of 4 source clock frequencies for
the timer (4096 Hz, 64 Hz, 1 Hz, or
counts down from a software-loaded 8-bit binary value. At the end of every countdown,
the timer sets the Timer Flag (TF). The TF may only be cleared by software. The
asserted TF can be used to generate an interrupt (INT). The interrupt may be generated
as a pulsed signal every countdown period or as a permanently active signal which
follows the condition of TF. Bit TI/TP is used to control this mode selection. When reading
the timer, the current countdown value is returned.
A programmable square wave is available at pin CLKOUT. Operation is controlled by the
CLKOUT control register at address 0Dh. Frequencies of 32.768 kHz (default), 1024 Hz,
32 Hz and 1 Hz can be generated for use as a system clock, microcontroller clock, input to
a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and
enabled at power-on. If disabled it becomes high-impedance.
The PCF8563 includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I
according to
The PCF8563 has an on-chip voltage-low detector (see
V
information is no longer guaranteed. The VL flag can only be cleared by software.
Bit VL is intended to detect the situation when V
battery operation. Should V
This will indicate that the time may be corrupted.
Fig 7. Voltage-low detection
low
, bit VL in the seconds register is set to indicate that the integrity of the clock
Table
25.
Rev. 05 — 17 July 2007
V
V
DD
low
DD
reach V
2
C-bus logic is initialized and all registers are reset
1
60
period of battery
operation
low
Hz), and enables or disables the timer. The timer
before power is re-asserted then bit VL is set.
DD
VL set
is decreasing slowly, for example under
normal power
operation
Figure
mgr887
t
7). When V
Real time clock/calendar
PCF8563
© NXP B.V. 2007. All rights reserved.
DD
drops below
5 of 32