pcf8534ah-1 NXP Semiconductors, pcf8534ah-1 Datasheet - Page 23

• Manufacturer Part Number: pcf8534ah-1
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 9 Load data pointer option 1
Table 10 Device select option 1
Table 11 Bank select option 1 (Input)
Table 12 Bank select option 2 (Output)
Table 13 Blink option 1
Table 14 Blink option 2
Note
1. Normal blinking is assumed when multiplex rates 1 : 3
7.9
The display controller executes the commands identified
by the command decoder. It contains the status registers
of the PCF8533 and co-ordinates their effects.
The controller is also responsible for loading display data
into the display RAM as required by the filling order.
1999 Jul 30
7 bit binary value of
0 to 79
3 bit binary value of 0 to 7
RAM bit 0
RAM bit 2
RAM bit 0
RAM bit 2
Off
2 Hz
1 Hz
0.5 Hz
Normal blinking
Alternation blinking
Universal LCD driver for low multiplex rates
or 1 : 4 are selected.
DESCRIPTION
STATIC
STATIC
Display controller
BLINK FREQUENCY
DESCRIPTION
BLINK MODE
(1)
RAM bits 0 and 1
RAM bits 2 and 3
RAM bits 0 and 1
RAM bits 2 and 3
1 : 2 MUX
1 : 2 MUX
P6 P5 P4 P3 P2 P1 P0
BITS
A2
BF1
0
0
1
1
BIT O
BIT A
BITS
BITS
BIT I
A1
0
1
0
1
0
1
BF0
0
1
0
1
A0
23
7.10
In large display configurations, up to 16 PCF8533s can be
distinguished on the same I
hardware subaddress (A0, A1 and A2) and the
programmable I
cascaded PCF8533s are synchronized they can share the
backplane signals from one of the devices in the cascade.
Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one
device need to be through-plated to the backplane
electrodes of the display. The other PCF8533s of the
cascade contribute additional segment outputs but their
backplane outputs are left open-circuit (see Fig.16).
The SYNC line is provided to maintain the correct
synchronization between all cascaded PCF8533s. This
synchronization is guaranteed after the Power-on reset.
The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments, or by the definition of a
multiplex mode when PCF8533s with different SA0 levels
are cascaded). SYNC is organized as an input/output pad;
the output selection being realized as an open-drain driver
with an internal pull-up resistor. A PCF8533 asserts the
SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times. Should
synchronization in the cascade be lost, it will be restored
by the first PCF8533 to assert SYNC. The timing
relationship between the backplane waveforms and the
SYNC signal for the various drive modes of the PCF8533
are shown in Fig.17.
The contact resistance between the SYNC pads of
cascaded devices must be controlled. If the resistance is
too high then the device will not be able to synchronize
properly. This is particularly applicable to COG
applications. Table 15 shows the limiting values for
contact resistance.
Table 15 SYNC contact resistance
NUMBER OF DEVICES
Cascaded operation
11 to 16
6 to 10
3 to 5
2
2
C-bus slave address (SA0). When
2
C-bus by using the 3-bit
MAXIMUM CONTACT
RESISTANCE
Product specification
6000
2200
1200
700
PCF8533