pcf8536 NXP Semiconductors, pcf8536 Datasheet - Page 14

• Manufacturer Part Number: pcf8536
• Description: Universal Lcd Driver For Low Multiplex Rates Including A 6 Channel Pwm Generator
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8536
Product data sheet
Table 13.
[1]
[2]
It is possible to make the internal oscillator signal available on pin OSCCLK by using the
oscillator-control command (see
bit. If not required, the pin OSCCLK should be left open or connected to V
the signal at pin OSCCLK is disabled and pin OSCCLK is in 3-state.
Clock output is only valid when using the internal oscillator. The signal will appear on the
OSCCLK pin.
An intermediate clock frequency is available at the OSCCLK pin. The duty cycle of this
clock varies with the chosen divide ratio.
Table 14.
[1]
[2]
[3]
External clock:
bit OSC (see
The OSCCLK signal must switch between the V
chip.
The system is designed for a 230 kHz clock or alternatively for using a 9.6 kHz clock. The
EFR bit determines the external clock frequency. The clock frequency (f
determines the LCD frame frequency, see
The PWM generator requires a 230 kHz clock to operate. If PWM is enabled and an
external clock of 9.6 kHz is selected, then the internal oscillator will automatically start and
be used for the PWM signal generation.
PD
power-down
power-up
PD
power-down
power-down
power-up
When RESET is active, the internal oscillator is off.
Special case. The PWM generator needs 230 kHz and must be enabled when PWM is enabled.
When RESET is active, the pin OSCCLK is in 3-state.
In this state, an external clock may be applied, but it is not a requirement.
9.6 kHz is the nominal frequency with q = 24, see
Internal oscillator on/off table
OSCCLK table
Table
All information provided in this document is subject to legal disclaimers.
In applications where an external clock must be applied to the PCF8536,
OSC
n.a.
internal oscillator
external oscillator off
OSC
n.a.
n.a.
internal oscillator
external oscillator n.a.
Universal LCD low multiplex driver with 6 channel PWM generator
10) has to be set logic 1. In this case pin OSCCLK becomes an input.
Rev. 1 — 6 October 2011
Table
PWM
n.a.
n.a.
on
on
COE
off
on
off
on
10) and configuring the clock output enable (COE)
Table
Table
SS
15.
15.
and the V
EFR
n.a.
n.a.
n.a.
9.6 kHz
230 kHz
EFR
n.a.
n.a.
n.a.
n.a.
9.6 kHz
230 kHz
DD
voltage supplied to the
PCF8536
© NXP B.V. 2011. All rights reserved.
clk(ext)
Internal
oscillator state
off
on
off
on
off
OSCCLK pin
3-state
V
3-state
9.6 kHz output
9.6 kHz input
230 kHz input
SS
DD
[2]
. At power-on
) in turn
[2]
14 of 74
[1]
[3]
[1]