pcf8832 NXP Semiconductors, pcf8832 Datasheet - Page 41

• Manufacturer Part Number: pcf8832
• Description: Pcf8832 Stn Rgb - 384 Output Column Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
11.2
The serial interface is also a 3-line bidirectional interface
for communication between the microcontroller and the
LCD driver chip. The three lines are: SCE (chip enable),
SCLK (serial clock) and SDI/SDO (serial data).
11.2.1
The interface write mode means that the microcontroller
writes commands and data to the PCF8832. Each data
packet contains a control bit D/C and a transmission byte.
If D/C is LOW, the byte that follows is interpreted as a
control byte.
The basic and the advanced protocols are supported. The
command set is given in Table 6. If D/C is HIGH, the byte
that follows is stored in the display data RAM. After every
data byte the address counter is incremented
automatically.
The serial interface is initialized when SCE is HIGH. In this
state, SCLK clock pulses have no effect and no power is
2002 Aug 16
handbook, full pagewidth
STN RGB - 384 output column driver
(1) Transmission byte may be a command byte or a data byte.
Serial interface (3-line)
W
RITE MODE
D/C
D/C
MSB
D7
transmission byte
D6
D5
transmission byte
D4
Fig.40 Serial data stream, write mode.
D3
D/C
D2
(1)
D1
transmission byte
LSB
D0
41
consumed by the serial interface. A falling edge on SCE
enables the serial interface and indicates the start of data
transmission.
Serial bus protocol (see Fig.41):
When SCE is HIGH, SCLK clocks are ignored. During
the HIGH time of SCE, the serial interface is initialized.
At the falling edge of SCE, SCLK must be LOW
SDI is sampled on the rising edge of SCLK
D/C indicates whether the byte is a command (D/C = 0)
or RAM data (D/C = 1); D/C is sampled with the first
rising edge of SCLK
If SCE stays LOW after the last bit of a command/data
byte, the serial interface expects the D/C bit of the next
byte at the next rising edge of SCLK
A reset pulse with RES interrupts the transmission (the
data being written into the RAM may be corrupted); the
registers are cleared, then if SCE is LOW after the rising
edge of RES, the serial interface is ready to receive the
D/C bit of a command/data byte.
D/C
transmission byte
Preliminary specification
MGW713
PCF8832