pcf8832 NXP Semiconductors, pcf8832 Datasheet - Page 7

• Manufacturer Part Number: pcf8832
• Description: Pcf8832 Stn Rgb - 384 Output Column Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7
7.1
The interface is the connection between the outside world
and PCF8832. One of five industrial standard interfaces
can be selected using the interface configuration inputs
PS2, PS1 and PS0.
7.2
It is possible to configure the PCF8832s to use external
voltages, see Table 2.
Table 1 Default configuration settings
Table 2 Analog circuit configuration
7.3
The on-chip oscillator provides the clock signal for the
display system. An external clock signal, if used, is
connected to the OSC input. In this case the internal
oscillator must be switched off by a software command.
To improve the timing accuracy there is an external
resistor option. If this option is used, the external resistor
must be connected between OSC and V
appropriate register must be set. If the internal resistor is
selected, the OSC input must be left open-circuit.
7.4
The Display Data RAM (DDRAM) is a 128
static RAM for display data storage. During RAM access,
data is transferred to the DDRAM via the interface.
7.5
The address counter sets the addresses of the display
data RAM for writing operations.
2002 Aug 16
ANALOG SWITCHING0
STN RGB - 384 output column driver
FUNCTIONAL DESCRIPTION
I/O buffer and interface
Configuration control
Oscillator
Display data RAM
Address counter
AOFF = 0
AOFF = 1
INPUT
CSCD
FSYN
LPOS
analog part active
analog part switched off,
analog voltages are input
through V
DEFAULT VALUE
EFFECT
COL
DD1
0
0
1
, V
and the
9
M
168-bit
7
7.6
The display is generated by continuously reading-out rows
of RAM data to the dot matrix LCD via the column outputs.
The display status (all dots on/off and normal/inverse
video) is set via the interface.
7.7
The command decoder identifies command words arriving
at the interface and routes the following data bytes to their
destination.
7.8
The voltage multiplier generates the required column
voltage V
external capacitor. If the capacitive DC-to-DC converter is
switched off by AOFF = 1, then V
externally.
7.9
The LCD power supply block generates the row voltage
level V
switched off by AOFF = 1, then V
an external source.
7.10
The internal reset circuit handles hardware and software
resets, provides the reset signal required internally and
controls the reset signal for the row driver IC.
7.11
The timing generator produces the various signals
required to coordinate the column driver with the row
driver.
7.12
The row driver IC is controlled completely by commands
from the column driver.
7.13
The LCD drive section includes 128
(C0 to C383) which should be connected directly to the
LCD. The column output signals are generated in
accordance with the data in the display latches. The data
are loaded from the display RAM when the corresponding
row signal is active. Unused column outputs should be left
open-circuit when less than 384 columns are required.
M
Display address counter
Command decoder
DC-to-DC converter
LCD power supply
Internal reset
Timing generator
Row driver control
Column drivers and data latches
(equivalent to
COL
. Pins CA1 and CA2 must be connected to an
V
------------ -
COL
2
). If the LCD power supply is
M
Preliminary specification
COL
must be supplied from
must be supplied
3 column outputs
PCF8832