pca8533 NXP Semiconductors, pca8533 Datasheet - Page 14

• Manufacturer Part Number: pca8533
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA8533
Product data sheet
7.5.1 Internal clock
7.5.2 External clock
7.5 Oscillator
7.6 Timing
7.7 Display register
7.8 Segment outputs
The internal logic and the LCD drive signals of the PCA8533 are timed by a frequency f
which either is derived from the built-in oscillator frequency f
frequency f
The clock frequency f
calculated as follows:
Table 6.
The internal oscillator is enabled by connecting pin OSC to V
from pin CLK provides the clock signal for cascaded PCA8533 in the system.
Pin CLK is enabled as an external clock input by connecting pin OSC to V
A clock signal must always be supplied to the device; removing the clock may freeze the
LCD in a DC state, which is not suitable for the liquid crystal.
The PCA8533 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the synchronization signal (SYNC) maintains the correct timing relationship
between all PCA8533 in the system. The timing also generates the LCD frame signal (f
whose frequency is derived as an integer division of the clock frequency f
applied to pin CLK from either the internal or an external clock.
The display register holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display register, the
LCD segment outputs and each column of the display RAM.
The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected
directly to the LCD. The segment output signals are generated in accordance with the
multiplexed backplane signals and with data residing in the display register. If less than
80 segment outputs are required, the unused segment outputs must be left open-circuit.
Nominal clock frequency (Hz)
1536
f
f
clk
fr
=
=
f
------- -
24
clk
f
------- -
64
osc
LCD frame frequency
clk(ext)
All information provided in this document is subject to legal disclaimers.
.
clk
Rev. 1 — 27 April 2011
determines the LCD frame frequency f
Universal LCD driver for low multiplex rates
LCD frame frequency (Hz)
64
osc
SS
or equals an external clock
fr
. In this case the output
(see
Table
PCA8533
© NXP B.V. 2011. All rights reserved.
clk
DD
(see
6) and is
.
Table
14 of 48
clk
6),
fr
)
,