pca82c200t NXP Semiconductors, pca82c200t Datasheet - Page 36

• Manufacturer Part Number: pca82c200t
• Description: 8-bit Microcontroller With On-chip Can
• Manufacturer: NXP Semiconductors

Philips Semiconductors
13.5.4
A command bit initiates an action within the transfer layer of the CAN-controller. The Command Register appears to the
CPU as a read/write memory, except for the bits CMR.0 (TR) to CMR.3 (COS), which return a HIGH if being read.
Table 33 Command Register (address 1)
Table 34 Description of the CMR bits
1996 Jun 27
8-bit microcontroller with on-chip CAN
RX0A
BIT
7
7
6
5
4
3
2
1
0
C
OMMAND
RX0A
RX1A
WUM
SLP
COS
RRB
AT
TR
SYMBOL
RX1A
R
EGISTER
6
(CMR)
RX0 Active. See Table 35; note 1.
RX1 Active. See Table 35; note 1.
Wake-up Mode (note 2). If the value of WUM is:
Sleep (note 3). If the value of SLP is:
Clear Overrun Status (note 4). If the value of COS is:
Release Receive Buffer (note 5). If the value of RRB is:
Abort Transmission (note 6). If the value of AT is:
Transmission Request (note 7). If the value of TR is:
HIGH (single ended), then the difference of the RX signals to the internal reference
voltage
LOW (differential), then the differential signal between RX0 and RX1 is used for wake
up.
HIGH (sleep), then the CAN-controller enters sleep mode if no CAN interrupt is
pending and there is no bus activity.
LOW (wake up), then the CAN-controller functions normally.
HIGH (clear), then the Data Overrun status bit is set to LOW (see Table 37).
LOW (no action), then there is no action.
HIGH (released), then the Receive Buffer attached to the CPU is released.
LOW (no action), then there is no action.
HIGH (present) and if not already in progress, a pending Transmission Request is
cancelled.
LOW (absent), then there is no action.
HIGH (present), then a message shall be transmitted.
LOW (absent), then there is no action.
WUM
5
1
2
AV
DD
is used for wake up.
SLP
4
36
COS
3
FUNCTION
RRB
2
AT
1
Product specification
P8xCE598
TR
0