pca82c200t NXP Semiconductors, pca82c200t Datasheet - Page 42

• Manufacturer Part Number: pca82c200t
• Description: 8-bit Microcontroller With On-chip Can
• Manufacturer: NXP Semiconductors

Philips Semiconductors
13.5.7
The Acceptance Code Register is part of the acceptance
filter of the CAN-controller. This register can be accessed
(read/write), if the Reset Request bit is set HIGH (present).
When a message is received which passes the
acceptance test and if there is an empty Receive Buffer,
then the respective Descriptor and Data Field
(see Fig.15) are sequentially stored in this empty buffer.
Data Overrun bit is set HIGH (overrun); see
Sections 13.5.5 and 13.5.6.
Table 41 Acceptance Code Register (address 4)
Table 42 Description of the ACR bits
13.5.8
The Acceptance Mask Register is part of the acceptance
filter of the CAN-controller.
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).
Table 43 Acceptance Mask Register (address 5)
Table 44 Description of the AMR bits
1996 Jun 27
In the event that there is no empty Receive Buffer, the
8-bit microcontroller with on-chip CAN
7 to 0
7 to 0
AM.7
AC.7
BIT
BIT
7
7
A
A
CCEPTANCE
CCEPTANCE
AC.7 to
AC.0
AM.7 to
AM.0
SYMBOL
SYMBOL
AM.6
AC.6
6
6
C
M
ODE
ASK
R
R
EGISTER
EGISTER
Acceptance Mask. If the Acceptance Mask bit is:
Acceptance Code. The Acceptance Code bits (AC.7 to AC.0) and the eight most
significant bits of the message's Identifier (ID.10 to ID.3) must be equal to those bit
positions which are marked relevant by the Acceptance Mask bits (AM.7 to AM.0).
The acceptance is given, if the following equation is satisfied:
(ID10 ... ID.3) = [(AC.7 ... AC.0) or (AM.7 ... AM.0)] = 1111 1111 B
HIGH (don’t care), then this bit position is ‘don’t care’ for the acceptance of a message.
LOW (relevant), then this bit position is ‘relevant’ for acceptance filtering.
AM.5
AC.5
5
5
(AMR)
(ACR)
AM.4
AC.4
4
4
42
When the complete message has been correctly received
the following occurs:
During transmission of a message which passes the
acceptance test, the message is also written to its own
Receive Buffer. If no Receiver Buffer is available, Data
Overrun is signalled because it is not known at the start of
a message whether the CAN-controller will lose arbitration
and so become a receiver of the message.
The Acceptance Mask Register qualifies which of the
corresponding bits of the acceptance code are ‘relevant’ or
‘don't care’ for acceptance filtering.
The Receive Buffer Status bit is set HIGH (full)
If the Receive Interrupt Enable bit is set HIGH (enabled),
the Receive Interrupt is set HIGH (set).
AM.3
AC.3
3
3
FUNCTION
FUNCTION
AM.2
AC.2
2
2
AM.1
AC.1
1
1
Product specification
P8xCE598
AM.0
AC.0
0
0