max5961 Maxim Integrated Products, Inc., max5961 Datasheet - Page 17

• Manufacturer Part Number: max5961
• Description: 0 To 16v, Quad, Hot-swap Controller With 10-bit Current And Voltage Monitor
• Manufacturer: Maxim Integrated Products, Inc.

Depending on the configuration of the Chx_EN1 and
Chx_EN2 bits, when V
and the ON_ input reaches its internal threshold, the
MAX5961 turns on the external n-channel MOSFET for
the corresponding channel, allowing power to flow to
the load. The channel is enabled depending on the out-
put of a majority function. Chx_EN1, Chx_EN2, and ON_
are the inputs to the majority function and the channel is
enabled when two or more of these inputs are 1.
Channel enabled = (Chx_EN1 x Chx_EN2) +
Table 4a. status1 Register Function
Table 3. chxen Register Format
Description:
Register Title:
Register Address:
Ch4_EN2
REGISTER
ADDRESS
bit 7
R/W
0x60
Hot-Swap Channels On-Off Control
Ch4_EN1
BIT RANGE
bit 6
R/W
______________________________________________________________________________________
with 10-Bit Current and Voltage Monitor
(Chx_EN1 x ON_) + (Chx_EN2 x ON_)
[3:0]
[5:4]
[7:6]
IN
is above the V
Channel enable bits
chxen
0x69
Ch3_EN2
0 to 16V, Quad, Hot-Swap Controller
ON_ Inputs State
1 = ON_ above 600mV channel enable threshold
0 = ON_ below 600mV channel enable threshold
Bit 0: ON1
Bit 1: ON2
Bit 2: ON3
Bit 3: ON4
Channel Grouping Mode (MODE Input)
00 = Grouped (MODE unconnected)
01 = Paired (MODE high)
10 = Independent (MODE low)
11 = (Not possible)
Voltage Critical Behavior (PROT Input)
00 = Assert ALERT upon UV/OV critical (same as UV/OV warning behavior)
01 = Assert ALERT and deassert PG_ upon UV/OV critical
10 = Assert ALERT, deassert PG_, and shutdown channel(s) upon UV/OV critical
11 = (Not possible)
bit 5
R/W
UVLO
Ch3_EN1
bit 4
R/W
threshold
Ch2_EN2
bit 3
R/W
The inputs ON_ and Chx_EN2 can be set externally; the
initial state of the Chx_EN2 bits in register chxen is set
by the state of the HWEN input when IN rises above
V
analog comparators with a 0.6V threshold. Whenever
V
ister status1[3:0] is set to 1. The inputs Chx_EN1 and
Chx_EN2 can be set using the I
Chx_EN1 bits have a default value of 0. This makes it
possible to enable or disable each of the MAX5961
channels independently with or without using the I
interface (see Tables 3, 4a, and 4b).
UVLO
ON_
Ch2_EN1
DESCRIPTION
is above 0.6V, the corresponding ON_ bit in reg-
bit 2
. The ON_ inputs connect to internal precision
R/W
Ch1_EN2
bit 1
R/W
Ch1_EN1
bit 0
R/W
2
C interface; the
AA (HWEN
00 (HWEN
VALUE
= high)
RESET
= low)
2
17
C