max5961 Maxim Integrated Products, Inc., max5961 Datasheet - Page 32

• Manufacturer Part Number: max5961
• Description: 0 To 16v, Quad, Hot-swap Controller With 10-bit Current And Voltage Monitor
• Manufacturer: Maxim Integrated Products, Inc.

0 to 16V, Quad, Hot-Swap Controller
with 10-Bit Current and Voltage Monitor
The voltage and current minimum- and maximum-value
records in register locations 0x10 through 0x2F can be
reset by writing a 1 to the appropriate location in regis-
ter peak_log_rst (see Table 36). The minimum-value
registers are reset to 0x3FF, and the maximum-value
registers are reset to 0x000.
As long as a bit in register peak_log_rst is 1, the corre-
sponding peak-detection registers are disabled and
are “cleared” to their power-up reset values. The volt-
age and current minimum- and maximum-detection
32
Table 37. Peak-Detection Hold-Control Register Format
Table 35. ADC Maximum Voltage Conversion Register Format (Low-Order Bits)
Table 36. Peak-Detection Reset-Control Register Format
Description:
Register Titles:
Register Addresses:
Description:
Register Title:
Register Address:
Description:
Register Title:
Register Address:
ch4_v_hld
ch4_v_rst
______________________________________________________________________________________
bit 7
bit 7
R/W
R/W
bit 7
R/W
Current Peak-Detection Registers
ch4_i_hld
ch4_i_rst
bit 6
bit 6
bit 6
R/W
R/W
R/W
Using the Voltage and
Reset control bits for peak-detection registers
peak_log_rst
0x73
Hold control bits for peak-detection registers; per signal
peak_log_hold
0x74
Maximum voltage conversion result, low-order bits [1:0]
max_ch1_mon_l
0x17
ch3_v_hld
ch3_v_rst
bit 5
bit 5
R/W
bit 5
R/W
R/W
ch3_i_rst
ch3_i_hld
bit 4
R/W
bit 4
R/W
bit 4
R/W
max_ch2_mon_l
0x1F
ch2_v_rst
ch2_v_hld
bit 3
R/W
bit 3
R/W
bit 3
R/W
register contents for each signal can be “held” by set-
ting bits in register peak_log_hold (see Table 37).
Writing a 1 to a location in register peak_log_hold locks
the register contents for the corresponding signal and
stops the min/max detection and logging; writing a 0
enables the detection and logging. Note that the peak-
detection registers cannot be cleared while they are
held by register peak_log_hold.
The combination of these two control registers allows
the user to monitor voltage and current peak-to-peak
values during a particular time period.
bit 2
ch2_i_rst
R/W
ch2_i_hld
bit 2
R/W
max_ch3_mon_l
0x27
bit 2
R/W
vmax_1
bit 1
R/W
ch1_v_rst
ch1_v_hld
bit 1
R/W
bit 1
R/W
max_ch4_mon_l
0x2F
vmax_0
bit 0
ch1_i_hld
R/W
ch1_i_rst
bit 0
R/W
bit 0
R/W
VALUE
RESET
RESET
VALUE
RESET
VALUE
0x00
0x00
0x00