max5961 Maxim Integrated Products, Inc., max5961 Datasheet - Page 41

• Manufacturer Part Number: max5961
• Description: 0 To 16v, Quad, Hot-swap Controller With 10-bit Current And Voltage Monitor
• Manufacturer: Maxim Integrated Products, Inc.

The acknowledge bit (ACK) is the 9th bit attached to
any 8-bit data word. The receiving device always gener-
ates an ACK. The MAX5961 generates an ACK when
receiving an address or data by pulling SDA low during
the 9th clock period (see Figure 9). When transmitting
data, such as when the master device reads data back
from the MAX5961, the MAX5961 waits for the master
device to generate an ACK. Monitoring ACK allows for
the detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if the receiving device is
busy or if a system fault has occurred. In the event of an
unsuccessful data transfer, the bus master should reat-
tempt communication at a later time. The MAX5961 gen-
erates a not acknowledge (NACK) after the slave
address during a software reboot or when receiving an
illegal memory address.
The send byte protocol allows the master device to
send one byte of data to the slave device (see Figure
8). The send byte presets a register pointer address for
a subsequent read or write. The slave sends a NACK
instead of an ACK if the master tries to send an
address that is not allowed. If the master sends a STOP
condition, the internal address pointer does not
change. The send byte procedure follows:
Figure 9. Acknowledge
TRANSMITTER
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit data byte.
RECEIVER
SDA BY
SDA BY
write bit (low).
SCL
CONDITION
START
S
______________________________________________________________________________________
with 10-Bit Current and Voltage Monitor
0 to 16V, Quad, Hot-Swap Controller
1
Acknowledge
Send Byte
2
The write byte/word protocol allows the master device
to write a single byte in the register bank or to write to a
series of sequential register addresses. The write byte
procedure follows:
To write a single byte to the register bank, only the 8-bit
command code and a single 8-bit data byte are sent.
The data byte is written to the register bank if the com-
mand code is valid.
The slave generates a NACK at step 5 if the command
code is invalid. The command code must be in the
range of 0x00 to 0x74. The internal address pointer
returns to 0x00 after incrementing from the highest reg-
ister address.
5) The addressed slave asserts an ACK on SDA.
6) The master sends a STOP condition.
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
3) The addressed slave asserts an ACK on SDA.
4) The master sends an 8-bit command code.
5) The addressed slave asserts an ACK on SDA.
6) The master sends an 8-bit data byte.
7) The addressed slave asserts an ACK on SDA.
8) The addressed slave increments its internal
9) The master sends a STOP condition or repeats
CLOCK PULSE FOR ACKNOWLEDGE
write bit (low).
address pointer.
steps 6, 7, and 8.
8
9
Write Byte
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