ADN8102-EVALZ Analog Devices, ADN8102-EVALZ Datasheet - Page 5

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ADN8102-EVALZ

Manufacturer Part Number
ADN8102-EVALZ
Description
3.75 Gbps Quad Bidirectional CX4 Equalizer
Manufacturer
Analog Devices
Datasheet
TIMING SPECIFICATIONS
Table 2. I
Parameter
f
t
t
t
t
t
t
t
t
t
t
C
SCL
HD:STA
SU:STA
LOW
HIGH
HD:DAT
SU:DAT
R
F
SU:STO
BUF
IO
SDA
SCL
t
F
2
C Timing Parameters
S
Min
0
0.6
0.6
1.3
0.6
0
10
1
1
0.6
1
5
t
HD:STA
t
LOW
t
HD:DAT
Max
400
N/A
N/A
N/A
N/A
N/A
N/A
300
300
N/A
N/A
7
t
t
SU:DAT
R
Unit
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
ns
pF
t
HIGH
Description
SCL clock frequency
Hold time for a start condition
Setup time for a repeated start condition
Low period of the SCL clock
High period of the SCL clock
Data hold time
Data setup time
Rise time for both SDA and SCL
Fall time for both SDA and SCL
Setup time for a stop condition
Bus free time between a stop and a start condition
Capacitance for each I/O pin
t
F
Figure 2. I
Rev. A | Page 5 of 32
t
SU:STA
2
C Timing Diagram
Sr
t
HD:STA
t
SU:STO
t
R
P
t
BUF
ADN8102
S

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