CY2305/CY2309 Cypress Semiconductor Corp., CY2305/CY2309 Datasheet

CY2305/CY2309

Manufacturer Part Number

CY2305/CY2309

Description

PLL Based Clock Distribution Device

Manufacturer

Cypress Semiconductor Corp.

Datasheet

1.CY2305CY2309.pdf (13 pages)

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Cypress Semiconductor Corporation

Document #: 38-07140 Rev. *C

Features

Functional Description

The CY2309 is a low-cost 3.3V zero delay buffer designed to

distribute high-speed clocks and is available in a 16-pin SOIC

or TSSOP package. The CY2305 is an 8-pin version of the

CY2309. It accepts one reference input, and drives out five

low-skew clocks. The -1H versions of each device operate at

• 10-MHz to 100-/133-MHz operating range, compatible

• Zero input-output propagation delay

• Multiple low-skew outputs

• Less than 200 ps cycle-cycle jitter, compatible with

• Test Mode to bypass phase-locked loop (PLL) (CY2309

• Available in space-saving 16-pin 150-mil SOIC or

• 3.3V operation

• Industrial temperature available

Block Diagram

REF

with CPU and PCI bus frequencies

Pentium -based systems

only [see “Select Input Decoding” on page 2])

4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil

SOIC package (CY2305)

— Output-output skew less than 250 ps

— Device-device skew less than 700 ps

— One input drives five outputs (CY2305)

— One input drives nine outputs, grouped as 4 + 4 + 1

(CY2309)

PLL

Select Input

Decoding

2309-1

•

MUX

3901 North First Street

Low-cost 3.3V Zero Delay Buffer

up to 100-/133-MHz frequencies, and have higher drive than

the -1 devices. All parts have on-chip PLLs which lock to an

input clock on the REF pin. The PLL feedback is on-chip and

is obtained from the CLKOUT pad.

The CY2309 has two banks of four outputs each, which can

be controlled by the Select inputs as shown in the “Select Input

Decoding” table on page 2. If all output clocks are not required,

BankB can be three-stated. The select inputs also allow the

input clock to be directly applied to the outputs for chip and

system testing purposes.

The CY2305 and CY2309 PLLs enter a power-down mode

when there are no rising edges on the REF input. In this state,

the outputs are three-stated and the PLL is turned off, resulting

in less than 12.0 A of current draw for commercial temper-

ature devices and 25.0 A for industrial temperature parts. The

CY2309 PLL shuts down in one additional case as shown in

the table below.

Multiple CY2305 and CY2309 devices can accept the same

input clock and distribute it. In this case, the skew between the

outputs of two devices is guaranteed to be less than 700 ps.

All outputs have less than 200 ps of cycle-cycle jitter. The input

to output propagation delay on both devices is guaranteed to

be less than 350 ps, and the output to output skew is

guaranteed to be less than 250 ps.

The CY2305/CY2309 is available in two/three different config-

urations, as shown in the ordering information (page 10). The

CY2305-1/CY2309-1 is the base part. The CY2305-1H/

CY2309-1H is the high-drive version of the -1, and its rise and

fall times are much faster than the -1s.

CLKOUT

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

•

San Jose

CLKA1

CLKA2

CLKB1

CLKB2

GND

REF

Pin Configuration

CLK2

CLK1

GND

REF

SOIC/TSSOP

CA 95134

Top View

SOIC

Revised December 14, 2002

•

CLKOUT

CLK4

CLK3

CLKOUT

CLKA4

CLKA3

GND

CLKB4

CLKB3

408-943-2600

CY2305

CY2309

2309-2

2309-3

Related parts for CY2305/CY2309

CY2305/CY2309 Summary of contents

Page 1

... The CY2305/CY2309 is available in two/three different config- urations, as shown in the ordering information (page 10). The CY2305-1/CY2309-1 is the base part. The CY2305-1H/ CY2309-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1s ...

Page 2

Pin Description for CY2309 Pin Signal [1] 1 REF [2] 2 CLKA1 [2] 3 CLKA2 GND [2] 6 CLKB1 [2] 7 CLKB2 [ [ [2] 10 CLKB3 [2] 11 CLKB4 12 GND ...

Page 3

REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal ...

Page 4

Maximum Ratings Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage (Except REF) ............–0. Input Voltage REF......................................... –0. Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices Parameter V Supply Voltage DD ...

Page 5

Switching Characteristics for CY2305SC-1H and CY2309SC-1H Commercial Temperature Devices Parameter Name t1 Output Frequency [6] Duty Cycle = [6] Duty Cycle = [6] t3 Rise Time [6] t Fall Time 4 t ...

Page 6

Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices Parameter Name t Output to Output Skew 5 t Delay, REF Rising Edge to 6A CLKOUT Rising Edge t Delay, REF Rising Edge to 6B CLKOUT Rising Edge t Device to Device ...

Page 7

Switching Waveforms (continued) All Outputs Rise/Fall Time 2.0V OUTPUT 0. Output-Output Skew 1.4V OUTPUT 1.4V OUTPUT t 5 Input-Output Propagation Delay INPUT V DD OUTPUT t 6 Device-Device Skew CLKOUT, Device 1 ...

Page 8

Typical Duty Cycle and I DD Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C 3.1 3.2 3.3 3.4 VDD (V) Duty Cycle ...

Page 9

Typical Duty Cycle and IDD Trends Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C 3.1 3.2 3.3 3.4 VDD (V) Duty Cycle ...

Page 10

Test Circuits Test Circuit # 0.1 F OUTPUTS V DD 0.1 F GND GND Ordering Information Ordering Code CY2305SC-1 CY2305SC-1T CY2305SI-1 CY2305SI-1T CY2305SC-1H CY2305SC-1HT CY2305SI-1H CY2305SI-1HT CY2305ZC-1 CY2305ZC-1T CY2309SC-1 CY2309SC-1T CY2309SI-1 CY2309SI-1T CY2309SC-1H CY2309SC-1HT CY2309SI-1H CY2309SI-1HT CY2309ZC-1H ...

Page 11

Package Diagrams Document #: 38-07140 Rev. *C 8-lead (150-Mil) SOIC S8 16-lead (150-Mil) Molded SOIC S16 CY2305 CY2309 51-85066-A 51-85068-A Page ...

Page 12

Package Diagrams (continued) 16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 Pentium is a registered trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: ...

Page 13

... Document History Page Document Title: CY2305/CY2309 Low-Cost 3.3V Zero Delay Buffer Document Number: 38-07140 REV. ECN NO. Issue Date ** 110249 10/19/01 *A 111117 03/01/02 *B 117625 10/21/02 *C 121828 12/14/02 Document #: 38-07140 Rev. *C Orig. of Change Description of Change SZV Change from Spec number: 38-00530 to 38-07140 CKN Added t6B row to the Switching Characteristics Table; also added the letter “ ...

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