CY2305/CY2309 Cypress Semiconductor Corp., CY2305/CY2309 Datasheet - Page 6

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CY2305/CY2309

Manufacturer Part Number
CY2305/CY2309
Description
PLL Based Clock Distribution Device
Manufacturer
Cypress Semiconductor Corp.
Datasheet
Document #: 38-07140 Rev. *C
Switching Characteristics for CY2305SI-1and CY2309SI-1 Industrial Temperature Devices
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices
Switching Waveforms
Duty Cycle Timing
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
Parameter
5
6A
6B
7
J
LOCK
1
3
4
5
6A
6B
7
8
J
LOCK
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge
Delay, REF Rising Edge to
CLKOUT Rising Edge
Device to Device Skew
Cycle to Cycle Jitter
PLL Lock Time
Output Frequency
Duty Cycle
Duty Cycle
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge
Delay, REF Rising Edge to
CLKOUT Rising Edge
Device to Device Skew
Output Slew Rate
Cycle to Cycle Jitter
PLL Lock Time
1.4V
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Name
Name
[6]
[6]
= t
= t
[6]
[6]
t
2
2
2
1.4V
[6]
t
t
[6]
[6]
1
1
t
[6]
[6]
[6]
[6]
1
[6]
[6]
[6]
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30-pF load
10-pF load
Measured at 1.4V, F
Measured at 1.4V, F
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
Measured at V
Measured at V
PLL Bypass Mode, CY2309 device
only.
Measured at V
pins of devices
Measured between 0.8V and 2.0V
using Test Circuit #2
Measured at 66.67 MHz, loaded
outputs
Stable power supply, valid clock
presented on REF pin
All outputs equally loaded
Measured at V
Measured at V
PLL Bypass Mode, CY2309 device
only.
Measured at V
pins of devices
Measured at 66.67 MHz, loaded
outputs
Stable power supply, valid clock
presented on REF pin
1.4V
Test Conditions
Description
DD
DD
DD
DD
DD
DD
/2 on the CLKOUT
/2 on the CLKOUT
/2
/2. Measured in
/2
/2. Measured in
out
out
= 66.67 MHz
< 50.0 MHz
Min.
Min.
40.0
45.0
10
10
1
1
1
Typ.
Typ.
50.0
50.0
0
5
0
0
5
0
133.33
Max.
±350
250
700
200
Max.
±350
60.0
55.0
1.50
1.50
8.7
1.0
100
250
700
200
8.7
1.0
CY2305
CY2309
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MHz
MHz
V/ns
Unit
Unit
ms
ms
ps
ps
ns
ps
ps
ns
ns
ps
ps
ns
ps
ps
%
%
[7]

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