CY2305/CY2309 Cypress Semiconductor Corp., CY2305/CY2309 Datasheet - Page 4

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CY2305/CY2309

Manufacturer Part Number
CY2305/CY2309
Description
PLL Based Clock Distribution Device
Manufacturer
Cypress Semiconductor Corp.
Datasheet
Document #: 38-07140 Rev. *C
Maximum Ratings
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Input Voltage (Except REF) ............–0.5V to V
DC Input Voltage REF......................................... –0.5V to 7V
Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Switching Characteristics for CY2305SC-1and CY2309SC-1 Commercial Temperature Devices
V
T
C
C
C
t
V
V
I
I
V
V
I
I
t1
t3
t
t
t
t
t
t
t
Notes:
PU
IL
IH
DD
DD
4
5
6A
6B
7
J
LOCK
5.
6.
7.
Parameter
A
DD
IL
IH
OL
OH
L
L
IN
Parameter
Parameter
(PD mode)
REF input has a threshold voltage of V
Parameter is guaranteed by design and characterization. Not 100% tested in production.
All parameters specified with loaded outputs.
Output Frequency
Duty Cycle
Rise Time
Fall Time
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge
Delay, REF Rising Edge to
CLKOUT Rising Edge
Device to Device Skew
Cycle to Cycle Jitter
PLL Lock Time
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Power Down Supply Current
Supply Current
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
Power-up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
[6]
[6]
Name
[6]
= t
Description
[6]
2
t
[6]
DD
1
[6]
[6]
/2.
[6]
[6]
[5]
[5]
[6]
[6]
30-pF load
10-pF load
Measured at 1.4V, F
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
Measured at V
Measured at V
Bypass Mode, CY2309 device only.
Measured at V
of devices
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock
presented on REF pin
Description
DD
V
V
I
I
I
I
REF = 0 MHz
Unloaded outputs at 66.67 MHz,
SEL inputs at V
OL
OH =
OH
OL
IN
IN
+ 0.5V
= 8 mA (–1)
= –12 mA (–1H)
Test Conditions
= 0V
= V
= –8 mA (–1)
12 mA (–1H)
DD
DD
DD
DD
Test Conditions
/2 on the CLKOUT pins
/2
/2. Measured in PLL
out
Storage Temperature ................................. –65 C to +150 C
Junction Temperature ................................................. 150 C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... > 2,000V
DD
= 66.67 MHz
Min.
40.0
10
10
1
Min.
0.05
Min.
3.0
2.0
2.4
0
Typ.
50.0
0
5
0
100.0
Max.
Max.
50.0
12.0
32.0
3.6
0.8
0.4
70
30
10
50
7
133.33
Max.
±350
60.0
2.50
2.50
100
250
700
200
8.7
1.0
CY2305
CY2309
Page 4 of 13
Unit
Unit
mA
ms
pF
pF
pF
MHz
MHz
V
V
V
V
V
Unit
C
A
A
A
ms
ns
ns
ps
ps
ns
ps
ps
%
[7]

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