tda8752b-03 NXP Semiconductors, tda8752b-03 Datasheet
tda8752b-03
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tda8752b-03 Summary of contents
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... ADC clock. The PLL jitter is minimized for high resolution PC graphics applications. An external clock can also be input to the ADC possible to set the TDA8752B serial bus address to four different values, when several TDA8752B ICs are used in a system, by means of the I example, two ICs used in an odd/even confi ...
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... MHz clk from analog input to digital output; full-scale; ramp input 110 MHz clk V = 2.5 V with ref 100 ppm/ C maximum 3 dB 250 amb input signal settling time <1 ns amb Rev. 03 — 21 July 2000 TDA8752B 2 C-bus Typ Max Unit 5.0 5.25 V 5.0 5.25 V 5.0 5.25 V 5.0 5.25 V 5.0 5. ...
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... Triple high-speed Analog-to-Digital Converter 110 Msps Conditions Min 100 f = 110 MHz; ramp input clk f = 66.67 kHz; ref f = 110 MHz clk 20 2.8 mm Rev. 03 — 21 July 2000 TDA8752B Typ Max Unit 4095 1.1 W 112 ps Sampling frequency (MHz) Version SOT317-2 110 © Philips Electronics N.V. 2000. All rights reserved ...
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... CLAMP RED CHANNEL GREEN CHANNEL BLUE CHANNEL HSYNCI TDA8752B REGULATOR 2 I C-bus; 1-bit (Hlevel HSYNC DEC1 DEC2 PWDWN Rev. 03 — 21 July 2000 TDA8752B V SSD OGND G AGND PLL DGND OGND R OGND B OGND PLL OUTPUTS ...
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... AGC ADC REGISTER 2 I C-bus: 8 bits (Or) V CCAR REGISTER 1 COARSE GAIN ADJUST 2 I C-bus: 7 bits (Cr) RGAINC Rev. 03 — 21 July 2000 TDA8752B ROR 8 OUTPUTS RBOT 2 I C-BUS FCE468 © Philips Electronics N.V. 2000. All rights reserved ...
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... I C-bus; phase selector A 2 bits (Vco C-bus C-bus; 5 bits (Pa) 1 bit (Cka) phase selector C-bus; 5 bits (Pb) Rev. 03 — 21 July 2000 TDA8752B INV 0 /180 CKADCO CLKADC MUX CKBO 2 I C-bus; 1 bit (Ckb) NCKBO MUX CKAO 2 I C-bus; 1 bit (Ckab) ...
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... BGAINC 24 BCLP 25 BDEC 26 V CCA(B) 27 BIN 28 AGND B 29 n.c. 30 Fig 4. Pin configuration. 9397 750 07338 Product specification Triple high-speed Analog-to-Digital Converter 110 Msps TDA8752BH Rev. 03 — 21 July 2000 TDA8752B CKREFO CCO( ...
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... I C-bus and 3-wire serial bus disable control input (disable at HIGH level) 38 select enable for 3-wire serial bus input (see Rev. 03 — 21 July 2000 TDA8752B 2 C-bus (active HIGH) and 3-wire Figure 10) © Philips Electronics N.V. 2000. All rights reserved ...
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... ADC output bit 4 76 red channel ADC output bit 5 77 red channel ADC output bit 6 78 red channel ADC output bit 7 (MSB) 79 red channel ADC output power supply Rev. 03 — 21 July 2000 TDA8752B © Philips Electronics N.V. 2000. All rights reserved ...
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... PLL coast command input 94 PLL reference clock input 95 digital power supply 96 PLL analog ground PLL 97 PLL filter input 98 PLL filter input 99 PLL analog power supply 100 not connected Rev. 03 — 21 July 2000 TDA8752B © Philips Electronics N.V. 2000. All rights reserved ...
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... LSB. The digitized video signal is always between code 0 and code 255 of 2 255 digitized video signal code 64 code 0 code 63.5 = 2.5 V (DC), with a maximum variation of ref Rev. 03 — 21 July 2000 TDA8752B Figure = 120 to 136 clamp programming FCE471 © Philips Electronics N.V. 2000. All rights reserved ...
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... N COARSE code 127 G (max) G (min ref 0.2 0.156 = 16 Rev. 03 — 21 July 2000 TDA8752B ref Figure 2 and 6). The three 7-bit Figure 6). A contrast control can be Figure 2 Figure 6). ADC output code ...
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... Triple high-speed Analog-to-Digital Converter 110 Msps ADC output code 255 G (max) 227 N COARSE 160 128 N FINE = 0 N FINE = 31 . NCOARSE ----- - ------------------------------------- - Rev. 03 — 21 July 2000 TDA8752B G NCOARSE G (min) V ref FCE473 © Philips Electronics N.V. 2000. All rights reserved. ( ...
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... Internet site to calculate the best PLL parameters possible to control (independently) the phase of the ADC clock and the phase of an additional clock output (which could be used to drive a second TDA8752B). For this, two serial interface-controlled digital phase-shift controllers are included (controlled by 5-bit registers, phase-shift controller steps are 11.25 deg each on the whole PLL frequency range) ...
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... When an RGB signal pixel frequency exceeding 100 to 200 MHz possible to follow one of the two possibilities given below: – Using one TDA8752B: the sampling rate can be reduced by a factor of two, by sampling the even pixels in the even frame and the odd pixels in the odd frame. ...
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... Philips Semiconductors CKREF CKREF Slave at 180 deg phase shift with respect to pin CKADCO of the master TDA8752B. Fig 9. Dual TDA8752B solution for pixel clock rate with a single phase adjustment (100 to 200 MHz). 2 8.7 I C-bus and 3-wire serial bus interface 2 The I and registers. Control pin DIS enables or disables the full serial interface function (disable at HIGH level) ...
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... Mode = 1, all the registers are programmed one after the other by giving this initial condition (XXX1 1111) as the subaddress state; thus, the registers are charged following the predefined sequence of 16 bytes (from subaddress 0000 to 1101). Rev. 03 — 21 July 2000 TDA8752B Table 4. Default value ...
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... V 1 – ----------------- - ref 2.5 V. ref Table = 0). FINE Gain correspondence (COARSE) Gain 0.825 2 for N = 32). COARSE Rev. 03 — 21 July 2000 TDA8752B ADC output underflow 0 ... 120 136 + 1 COARSE 32 512 N – FINE 6. The gain is linear with reference to the full-scale (V) i 1.212 ...
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... Triple high-speed Analog-to-Digital Converter 110 Msps Gain correspondence (FINE) Gain 0.825 0.878 = 0. FINE Table 8. Charge pump current control Ip1 Rev. 03 — 21 July 2000 TDA8752B full-scale (V) i 1.212 1.139 2 C-bus control bits Ip0 Current ( A) 0 6. 100 ...
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... Product specification Triple high-speed Analog-to-Digital Converter 110 Msps VCO register bits Vco0 Rev. 03 — 21 July 2000 TDA8752B Z0 Resistance ( high impedance 1 128 VCO gain (MHz/V) ...
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... Product specification Triple high-speed Analog-to-Digital Converter 110 Msps Table 11). Concerning the PHASEB register Rev. 03 — 21 July 2000 TDA8752B 2 C-bus programming 11.25 0 337.5 1 348.75 © Philips Electronics N.V. 2000. All rights reserved ...
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... The I Bits ‘A2’ and ‘A1’ are fixed by the potential on pins ADD1 and ADD2. Thus, four TDA8752Bs can be used on the same system, using the addresses for ADD1 and ADD2 with the I is not possible to read the data in the register. The timing and protocol for the I are standard ...
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For the 3-wire serial bus the first byte refers to the register address which is programmed. The second byte refers to the data to be sent to the chosen register (see Using the 3-wire serial ...
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... Parameter thermal resistance from junction to ambient , 4. 4. SSD and unless otherwise specified. CCD CCO amb Conditions Rev. 03 — 21 July 2000 TDA8752B Conditions Min Max 0.3 +7.0 0.3 +7.0 0.3 +7.0 0.3 +7.0 1.0 +1.0 1.0 +1.0 1.0 +1.0 1.0 +1.0 referenced 0.3 +7.0 to AGND 10 1.0 1 ...
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... V = 2.5 V with 100 ppm/ C ref maximum variation HSYNC active; capacitors on pins 8, 16 and corresponding to full-scale output f = 110 MHz; square wave 110 MHz; square wave i Rev. 03 — 21 July 2000 TDA8752B = V referenced to DGND CCD ( referenced to CCO connected together ...
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... MHz; see Table 18 clk when coast mode is aborted in start-up conditions amb from IC analog input to digital output; ramp input 110 MHz clk Rev. 03 — 21 July 2000 TDA8752B = V referenced to DGND CCD ( referenced to CCO connected together ...
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... L referenced to CKADCO Rev. 03 — 21 July 2000 TDA8752B = V referenced to DGND CCD ( referenced to CCO connected together typical SSD amb Min Typ Max 0 ...
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... with 10 k resistor with 10 k resistor repeated start f = 100 kHz SCL f = 100 kHz SCL Rev. 03 — 21 July 2000 TDA8752B = V referenced to DGND CCD ( referenced to CCO connected together typical SSD amb Min ...
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... HIGH 50% for t and t ; switch S1 connected to GND for t CCD dLZ dZL Rev. 03 — 21 July 2000 TDA8752B 1.4 V 2 h(o) 2 FCE475 50% t dZH 50% LOW V CCD S1 3.3 k TDA8752B FCE476 and t . dHZ dZH © Philips Electronics N.V. 2000. All rights reserved ...
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... Rev. 03 — 21 July 2000 TDA8752B I Z Long-term time jitter RMS-value peak-to-peak (ps) value (ns) 100 8 593 3.56 200 4 255 1.53 400 4 173 1.04 200 4 200 1.2 700 2 122 0.73 400 4 115 0 ...
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... V DDD n.c. ADD1 TCK DIS V SSD 2 ADD2 TDO SEN I C/3W 4.7 k SDA SCL V DDD Rev. 03 — 21 July 2000 TDA8752B PWDWN CKBO OE CKADCO V CCO(PLL OGND PLL DGND CKAO CKREFO 80 V CCO( ...
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... scale (1) ( 0.25 20.1 14.1 24.2 18.2 0.65 1.95 0.14 19.9 13.9 23.6 17.6 REFERENCES JEDEC EIAJ MO-112 Rev. 03 — 21 July 2000 TDA8752B detail (1) ( 1.0 0.8 1.0 0.2 0.15 0.1 0.6 0.4 0.6 EUROPEAN ISSUE DATE PROJECTION ...
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... Product specification Triple high-speed Analog-to-Digital Converter 110 Msps parallel to the transport direction of the printed-circuit board; transport direction of the printed-circuit board. Rev. 03 — 21 July 2000 TDA8752B © Philips Electronics N.V. 2000. All rights reserved ...
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... Product specification Triple high-speed Analog-to-Digital Converter 110 Msps methods [3] , SO, SOJ Rev. 03 — 21 July 2000 TDA8752B Soldering method Wave Reflow not suitable suitable [2] not suitable ...
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... Rev Date CPCN Description 3 20000721 Product specification 2 20000110 Preliminary specification 1 19991111 Objective specification 9397 750 07338 Product specification Triple high-speed Analog-to-Digital Converter 110 Msps Rev. 03 — 21 July 2000 TDA8752B © Philips Electronics N.V. 2000. All rights reserved ...
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... Philips’ system provided the system conforms to the I specification defined by Philips. This specification can be ordered using the code 9398 393 40011. Rev. 03 — 21 July 2000 TDA8752B Philips Semiconductors assumes 2 C components 2 C components conveys a license ...
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... United Kingdom: Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: Tel. +381 11 3341 299, Fax. +381 11 3342 553 Internet: http://www.semiconductors.philips.com (SCA70) Rev. 03 — 21 July 2000 TDA8752B © Philips Electronics N.V. 2000. All rights reserved ...
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... Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 21 July 2000 Document order number: 9397 750 07338 Triple high-speed Analog-to-Digital Converter 110 Msps Printed in The Netherlands TDA8752B ...