tda8366h NXP Semiconductors, tda8366h Datasheet - Page 9

• Manufacturer Part Number: tda8366h
• Description: I2c-bus Controlled Pal/ntsc Tv Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
Vision IF amplifier
The IF-amplifier contains 3 AC-coupled control stages with
a total gain control range which is in excess of 66 dB. The
sensitivity of the circuit is comparable with that of modern
IF-ICs. The reference carrier for the video demodulator is
obtained by means of passive regeneration of the picture
carrier. The external reference tuned circuit is the only
remaining adjustment of the IC.
The polarity of the demodulator can be switched via the
I
positive and negative modulated signals.
The AFC-circuit is driven with the same reference signal as
the video demodulator. To avoid that the video content
disturbs the AFC operation a sample-and-hold circuit is
applied for signals with negative modulation. The capacitor
for this function is internal. The AFC information is supplied
to the tuning system via the I
The AGC-detector operates on top-sync or top white-level
depending on the polarity of the demodulator. The
demodulation polarity is switched via the I
AGC detector time-constant capacitor is connected
externally (this mainly because of the flexibility of the
application). The time-constant of the AGC system during
positive modulation is rather long to avoid visible variations
of the signal amplitude. To obtain an acceptable speed of
the AGC system a circuit has been included which detects
whether the AGC detector is activated every frame period.
When during 3 frame periods no action is detected the
speed of the system is increased.
The circuit contains a video identification circuit which is
independent of the synchronization circuit. Therefore
search tuning is possible when the display section of the
receiver is used as a monitor. The identification output is
supplied to the tuning system via the I
information of this identification circuit can also be used to
switch the phase-1 (
is received so that a stable OSD display is obtained. The
coupling of the video identification circuit with the
can be switched on and off via the I
January 1995
2
C-bus in such a way that the circuit is suitable for both
I
processor
2
C-bus controlled PAL/NTSC TV
1
) loop to a low gain when no signal
2
C-bus.
2
C-bus.
2
C-bus. The
2
C-bus. The
1
loop
9
Synchronization circuit
The sync separator is preceded by a controlled amplifier
which adjusts the sync pulse amplitude to a fixed level.
These pulses are fed to the slicing stage which is operating
at 50% of the amplitude.
The separated sync pulses are fed to the first phase
detector and to the coincidence detector. This coincidence
detector is only used to detect whether the line oscillator is
synchronized and not for transmitter identification. The first
Phase-Locked Loop (PLL) has a very high-statical
steepness so that the phase of the picture is independent
of the line frequency.
The line oscillator is running at twice the line frequency.
The oscillator capacitor is internal. Because of the spreads
of internal components an automatic adjustment circuit
has been added to the IC. It compares the oscillator
frequency with that of the crystal oscillator in the colour
decoder.
To protect the horizontal output transistor the horizontal
drive is switched-off when a power-on-reset is detected.
The frequency of the oscillator is calibrated again when all
subaddress bytes have been sent. When the oscillator has
the right frequency the calibration stops and the horizontal
drive is switched-on again via the soft start procedure
(standby bit in normal mode). When the IC is switched-on
the same procedure is followed.
When the coincidence detector indicates an out-of-lock
situation the calibration procedure is repeated.
The circuit has a second control loop to generate the drive
pulses for the horizontal driver stage. During the start-up
procedure the duty cycle of the horizontal output pulse
increases from 0 to 50% in approximately 100 lines.
The vertical sawtooth generator drives the vertical output
and EW correction drive circuits. The geometry processing
circuits provide control of horizontal shift, EW width, EW
parabola/width ratio, EW corner/parabola ratio, trapezium
correction, vertical shift, vertical slope, vertical amplitude,
and the S-correction. All these controls can be set via the
I
2
C-bus. The geometry processor has a differential current
Objective specification
TDA8366