uda1338h-n1 NXP Semiconductors, uda1338h-n1 Datasheet - Page 45

• Manufacturer Part Number: uda1338h-n1
• Description: Multichannel Audio Coder-decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 67:
V
f
[1]
[2]
[3]
[4]
9397 750 14389
Product data sheet
Symbol
I
SCL timing
f
t
t
t
t
SDA timing
t
t
t
t
t
t
t
C
s
2
SCL
LOW
HIGH
r
f
BUF
SU;STA
HD;STA
SU;DAT
HD;DAT
SU;STO
SP
DDD
Fig 16. System clock timing
= 48 kHz; unless otherwise specified.
C-bus interface timing; see
b
The system clock should not exceed 58 MHz in any mode.
The bit clock frequency should not exceed 256 times the corresponding sampling frequency.
C
To be suppressed by the input filter.
= V
b
is the total capacitance for each bus line.
DDA(AD)
Timing
Parameter
SCL clock frequency
SCL LOW time
SCL HIGH time
rise time SDA and SCL
fall time SDA and SCL
bus free time between STOP and
START condition
set-up time repeated START
hold time START condition
data set-up time
data hold time
set-up time STOP condition
pulse width of spikes
capacitive load for each bus line
= V
…continued
DDA(AD)
= 2.7 V to 3.6 V; T
Figure 20
t
CWH
T
sys
t
CWL
amb
Rev. 03 — 16 February 2005
= 20 C to +85 C; typical timing specified at sampling frequency
Conditions
[3]
[3]
[4]
Min.
0
1.3
0.6
20 + 0.1C
20 + 0.1C
1.3
0.6
0.6
100
0
0.6
0
-
Multichannel audio coder-decoder
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
b
b
mgr984
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
UDA1338H
Max.
400
-
-
300
300
-
-
-
-
-
-
50
400
45 of 54
Unit
kHz
ns
ns
ns
ns
pF
s
s
s
s
s
s
s