uda1355h-n2 NXP Semiconductors, uda1355h-n2 Datasheet - Page 55

• Manufacturer Part Number: uda1355h-n2
• Description: Stereo Audio Codec With Spdif Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
12.2.4
Table 65 Register address 30H
Table 66 Description of register bits (address 30H)
2003 Apr 10
Symbol
Default
Symbol
Default
3 and 2
1 and 0 SLICER_SEL[1:0] SPDIF source select. Value to select an IEC 60958 input channel:
11 to 2
15 to 5
Stereo audio codec with SPDIF interface
BIT
BIT
BIT
BIT
1
0
4
SPDIF
DC_SKIP
HP_EN_DEC
PON_SPDI
SYMBOL
15
SYMBOL
0
7
0
INPUT SETTINGS
14
0
6
0
reserved
DC filter skip. If this bit is logic 0 then the DC filter is enabled; if this bit is logic 1 then the
DC filter is disabled. The DC filter is at the output of the comb filter just before the
decimator. This DC filter compensates for the DC offset added in the ADC (to remove idle
tones from the audio band). This DC offset must not be amplified in order to prevent
clipping.
High-pass enable. If this bit is logic 0 then the high-pass is disabled; if this bit is logic 1
then the high-pass is enabled. The high-pass is a DC filter which is at the output of the
decimation filter (running at f
reserved
Power control SPDIF input. If this bit is logic 0 then the SPDIF input is switched to
Power-down mode; if this bit is logic 1 then the SPDIF input is switched to power-on
mode.
reserved
00 = IEC 60958 input from pin SPDIF0
01 = IEC 60958 input from pin SPDIF1
10 = IEC 60958 input from pin SPDIF2
11 = IEC 60958 input from pin SPDIF3
13
0
5
0
PON_SPDI
12
0
4
1
s
55
).
11
0
3
0
DESCRIPTION
DESCRIPTION
10
0
2
0
SLICER_SEL1
9
0
1
0
Preliminary specification
UDA1355H
SLICER_SEL0
8
0
0
0