pca9575 NXP Semiconductors, pca9575 Datasheet
pca9575
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pca9575 Summary of contents
Page 1
... PCA9575 has built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where communication between incompatible I/Os is required. The core of PCA9575 can operate at a voltage as low as 1.1 V while each I/O bank can operate in the range 1 3.6 V. Bus hold with programmable on-chip pull-up or pull-down feature for I/Os is also provided. The output stage consists of two banks each of 8-bit confi ...
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... The PCA9575 is available in 24-pin TSSOP, 28-pin TSSOP and HWQFN24 packages, and is specified over the +85 C industrial temperature range. The 28-pin package provides four address select pins, allowing PCA9575 devices to be connected with 16 different addresses on the same I 2. Features ...
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... Ordering information Table 1. Ordering information Type number Topside mark PCA9575PW2 PCA9575PW2 PCA9575PW1 PA9575PW1 PCA9575HF 575F PCA9575_1 Product data sheet 2 16-bit I C-bus and SMBus, level translating, low voltage GPIO Package Name Description TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm TSSOP24 plastic thin shrink small outline package ...
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... C-bus and SMBus, level translating, low voltage GPIO PCA9575 2 I C-BUS/SMBus INPUT FILTER POWER-ON RESET Remark: All I/Os are set to inputs at power-up and RESET. Block diagram of PCA9575 Rev. 01 — 2 October 2008 PCA9575 8-bit INPUT/ OUTPUT PORTS BANK 1 write pulse read pulse CONTROL ...
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... CK output port register input port register DD(IO) 100 k polarity inversion register Rev. 01 — 2 October 2008 PCA9575 output port register data V DD(IO) P0_0 to P0_7 P1_0 to P1_7 Q2 ESD protection diode V SS input port register data INTERRUPT to INT MASK polarity inversion register data 002aad566 © ...
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... Transparent top view Rev. 01 — 2 October 2008 PCA9575 RESET P0_0 4 25 P0_1 P0_2 P0_3 7 22 PCA9575PW2 DD(IO P0_4 P0_5 11 18 P0_6 P0_7 INT 14 15 002aad563 Pin configuration for TSSOP28 ...
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... Rev. 01 — 2 October 2008 PCA9575 Type Description I address input 0 power supply supply voltage I active LOW reset input I/O port 0 input/output 0 I/O port 0 input/output 1 I/O port 0 input/output 2 I/O port 0 input/output 3 I address input 1 power supply I/O supply voltage for bank 0 ...
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... PCA9575 as shown in Fig 6. The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while logic 0 selects a write operation. The slave address for the 28-pin version of the PCA9575 is shown in Fig 7. PCA9575_1 Product data sheet ...
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... NXP Semiconductors 7.3 Command register Following the successful acknowledgement of the slave address + R/W bit, the bus master will send a byte to the PCA9575, which will be stored in the Command register. Fig 8. The lowest 4 bits are used as a pointer to determine which register will be accessed. Only a Command register code with the 4 least significant bits equal to the 16 allowable values as defi ...
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... After a restart, the device address is sent again but this time, the least significant bit is set to logic 1. Data from the register defined by the command byte will then be sent by the PCA9575. Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read using the auto-increment feature ...
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... Input port 0 register data 0 = Input port 0 register data retained (default value Input port 0 register data inverted Description inverts polarity of Input port 1 register data 0 = Input port 1 register data retained (default value Input port 1 register data inverted PCA9575 © NXP B.V. 2008. All rights reserved ...
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... Register 6 will have no effect on the I/O bank 0 (default value enables selection of pull-up/pull-down using Register 6 R/W 0* allows user to enable/disable the bus-hold feature for the I/O bank 0 pins 0 = disables bus-hold feature (default value enables bus-hold feature Rev. 01 — 2 October 2008 PCA9575 © NXP B.V. 2008. All rights reserved ...
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... Register 7 will have no effect on the I/O bank 0 (default value enables selection of pull-up/pull-down using Register 7 R/W 0* allows user to enable/disable the bus-hold feature for the I/O bank 1 pins 0 = disables bus-hold feature (default value enables bus-hold feature Rev. 01 — 2 October 2008 PCA9575 © NXP B.V. 2008. All rights reserved ...
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... Register 5 is logic 1 R selects a 100 k pull-down resistor for that I/O pin R selects a 100 k pull-up resistor for that I/O pin (default R/W 1* value) R/W 1* R/W 1* R/W 1* R/W 1* Rev. 01 — 2 October 2008 PCA9575 © NXP B.V. 2008. All rights reserved ...
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... R/W 1* C1.1 R/W 1* C1.0 R/W 1* Rev. 01 — 2 October 2008 PCA9575 Description configures the direction of the I/O pins 0 = corresponding port pin enabled as an output 1 = corresponding port pin configured as input (default value) Description configures the direction of the I/O pins 0 = corresponding port pin enabled as an output 1 = corresponding port pin configured as input (default value) © ...
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... Register 11 - Output port 1 register (address 0Bh) bit description Symbol Access Value O1.7 R/W 0* O1.6 R/W 0* O1.5 R/W 0* O1.4 R/W 0* O1.3 R/W 0* O1.2 R/W 0* O1.1 R/W 0* O1.0 R/W 0* Rev. 01 — 2 October 2008 PCA9575 Description reflects outgoing logic levels of pins defined as outputs by Register 8 Description reflects outgoing logic levels of pins defined as outputs by Register 9 © NXP B.V. 2008. All rights reserved ...
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... Register 13 - Interrupt mask port 1 register (address 0Dh) bit description Symbol Access Value M1.7 R/W 1* M1.6 R/W 1* M1.5 R/W 1* M1.4 R/W 1* M1.3 R/W 1* M1.2 R/W 1* M1.1 R/W 1* M1.0 R/W 1* Rev. 01 — 2 October 2008 PCA9575 Description enable or disable interrupts 0 = enable interrupt 1 = disable interrupt (default value) Description enable or disable interrupts 0 = enable interrupt 1 = disable interrupt (default value) © NXP B.V. 2008. All rights reserved ...
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... Power-on reset When power is applied reset condition until V and the PCA9575 registers and state machine will initialize to their default states. The power-on reset typically completes the reset and enables the part by the time the power supply is above V supply necessary to lower it below 0.2 V. ...
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... Once the General Call address has been sent and acknowledged, the master sends 1 byte. The value of the byte must be equal to 06h (1000 0011).The PCA9575 acknowledges this value only. If the byte is not equal to 06h, the PCA9575 does not acknowledge it. If more than 1 byte of data is sent, the PCA9575 does not acknowledge anymore ...
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... C-bus and SMBus, level translating, low voltage GPIO 2 C-bus SDA SCL data line stable; data valid Bit transfer Figure 10). S START condition Figure 11). Rev. 01 — 2 October 2008 PCA9575 Figure 9). change of data allowed mba607 P STOP condition © NXP B.V. 2008. All rights reserved. SDA SCL mba608 ...
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... SLAVE SLAVE TRANSMITTER/ RECEIVER TRANSMITTER RECEIVER data output by transmitter data output by receiver SCL from master 1 S START condition 2 C-bus Rev. 01 — 2 October 2008 PCA9575 MASTER MASTER TRANSMITTER/ MULTIPLEXER RECEIVER SLAVE not acknowledge acknowledge 2 8 clock pulse for acknowledgement 2 I C-BUS 002aaa966 9 002aaa987 © ...
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... NXP Semiconductors 9. Bus transactions Data is transmitted to the PCA9575 registers using ‘Write Byte’ transfers (see and Figure Data is read from the PCA9575 registers using ‘Read Byte’ transfers (see Figure 16). SCL (1) slave address SDA START condition ...
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... A DATA 1 R/W acknowledge from slave Rev. 01 — 2 October 2008 PCA9575 (cont.) A data from register A DATA (last byte) no acknowledge from master DATA 4 data from port A DATA 4 acknowledge from master © NXP B.V. 2008. All rights reserved ...
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... Parameter supply voltage input/output supply voltage 0 input/output supply voltage 1 input/output current input current supply current ground supply current total power dissipation storage temperature ambient temperature Rev. 01 — 2 October 2008 PCA9575 = 3.6 V SUBSYSTEM 4 (e.g., RF module) CTRL SUBSYSTEM 1 (e.g., temp. sensor) INT RESET SUBSYSTEM 2 (e.g., counter) A ...
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... OH DD(IO 1.1 V DD(IO 3 3.6 V; DD(IO)0 DD(IO DD(IO)0 I DD( DD(IO 1 3.6 V DD( DD(IO 1 3.6 V DD(IO 3 3.6 V; DD(IO)0 DD(IO Rev. 01 — 2 October 2008 PCA9575 = +85 C; unless amb Min Typ Max 1.1 - 3.6 1.1 - 3.6 1.1 - 3.6 - 135 200 - 0. 0. 0.7 1.0 DD 0.5 - +0.3V 0. ...
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... PCA9575_1 Product data sheet 2 16-bit I C-bus and SMBus, level translating, low voltage GPIO …continued = 1 3 DD(IO)1 Conditions DD(IO)1 Conditions Rev. 01 — 2 October 2008 PCA9575 = +85 C; unless SS amb Min Typ 0 ...
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... DD(IO)0 DD(IO 1 DD(IO)0 DD( Figure 19 Figure HD;DAT HIGH SU;DAT Rev. 01 — 2 October 2008 PCA9575 = +85 C; unless SS amb Standard-mode Fast-mode C-bus Min Max Min - 350 - - 300 - 150 - 150 ...
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... Fig 20. Test circuitry for switching times PCA9575_1 Product data sheet 2 16-bit I C-bus and SMBus, level translating, low voltage GPIO START PULSE DUT GENERATOR R T Rev. 01 — 2 October 2008 PCA9575 ACK or read cycle rst(SDA w(rst) t rst(GPIO output off 2V DD open V SS ...
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... REFERENCES JEDEC JEITA MO-153 Rev. 01 — 2 October 2008 detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION PCA9575 SOT355 ( 0.5 8 0.1 o 0.2 0 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2008. All rights reserved ...
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... REFERENCES JEDEC JEITA MO-153 Rev. 01 — 2 October 2008 detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION PCA9575 SOT361 ( 0.8 8 0.1 o 0.5 0 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2008. All rights reserved ...
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... 2.5 scale (1) ( 4.1 2.25 4.1 2.25 0.5 2.5 3.9 1.95 3.9 1.95 REFERENCES JEDEC JEITA - - - MO-220 Rev. 01 — 2 October 2008 PCA9575 detail 0.5 2.5 0.1 0.05 0.05 0.1 0.3 EUROPEAN PROJECTION SOT994-1 c ISSUE DATE 07-02-07 07-03-03 © NXP B.V. 2008. All rights reserved ...
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... Inspection and repair • Lead-free soldering versus SnPb soldering 17.3 Wave soldering Key characteristics in wave soldering are: PCA9575_1 Product data sheet 2 16-bit I C-bus and SMBus, level translating, low voltage GPIO Rev. 01 — 2 October 2008 PCA9575 © NXP B.V. 2008. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 24. Rev. 01 — 2 October 2008 PCA9575 Figure 24) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © NXP B.V. 2008. All rights reserved. ...
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... Inter-Integrated Circuit bus Integrated Circuit Light Emitting Diode Low Pass Machine Model Programmable Logic Controller Power-On Reset Redundant Array of Independent Discs Radio Frequency System Management Bus Rev. 01 — 2 October 2008 PCA9575 peak temperature time 001aac844 © NXP B.V. 2008. All rights reserved ...
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... Revision history Document ID Release date PCA9575_1 20081002 PCA9575_1 Product data sheet 2 16-bit I C-bus and SMBus, level translating, low voltage GPIO Data sheet status Change notice Product data sheet - Rev. 01 — 2 October 2008 PCA9575 Supersedes - © NXP B.V. 2008. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 2 October 2008 PCA9575 © NXP B.V. 2008. All rights reserved ...
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... Handling information . . . . . . . . . . . . . . . . . . . 32 Soldering of SMD packages . . . . . . . . . . . . . . 32 Introduction to soldering Wave and reflow soldering . . . . . . . . . . . . . . . 32 Wave soldering Reflow soldering Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . 35 Legal information . . . . . . . . . . . . . . . . . . . . . . 36 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 36 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Disclaimers Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Contact information . . . . . . . . . . . . . . . . . . . . 36 Contents Date of release: 2 October 2008 Document identifier: PCA9575_1 All rights reserved. ...