pca9626 NXP Semiconductors, pca9626 Datasheet - Page 33

• Manufacturer Part Number: pca9626
• Description: 24-bit Fm+ I2c-bus 100 Ma 40 V Led Driver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
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PCA9626_1
Product data sheet
Fig 18. Definition of timing
Fig 19. I
t
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region of SCL’s falling edge.
The maximum t
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
C
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
VD;DAT
b
SDA
SCL
= total capacitance of one bus line in pF.
Rise and fall times refer to V
= minimum time for SDA data out to be valid following SCL LOW.
2
C-bus timing diagram
P
protocol
t
SDA
SCL
BUF
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t
S
t
SU;STA
t
BUF
condition
t
START
HD;STA
t
LOW
(S)
t
HD;STA
IL
f
.
and V
t
LOW
t
r
t
t
r
HD;DAT
MSB
bit 7
(A7)
IH
t
.
HIGH
t
SU;DAT
Rev. 01 — 2 June 2009
t
f
t
1 / f
HIGH
bit 6
(A6)
SCL
t
t
HD;DAT
f
t
SU;DAT
bit 1
(D1)
t
VD;DAT
24-bit Fm+ I
Sr
(D0)
bit 0
t
SU;STA
t
t
VD;ACK
HD;STA
2
f
acknowledge
C-bus 100 mA 40 V LED driver
) for the SDA output stage is specified at
(A)
t
SU;STO
IL
of the SCL signal) in order to
002aab285
t
SP
condition
t
SU;STO
STOP
PCA9626
(P)
© NXP B.V. 2009. All rights reserved.
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P
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