pca9665 NXP Semiconductors, pca9665 Datasheet - Page 65

• Manufacturer Part Number: pca9665
• Description: Fm+ Parallel Bus To I2c-bus Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
9. Characteristics of the I
PCA9665_2
Product data sheet
9.1.1 START and STOP conditions
9.1 Bit transfer
9.2 System configuration
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
Fig 28. Bit transfer
Fig 29. Definition of START and STOP conditions
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
START condition
2
SDA
SCL
Figure
C-bus
S
Rev. 02 — 7 December 2006
29).
Figure
data valid
data line
stable;
30).
Figure
allowed
change
of data
28).
Fm+ parallel bus to I
STOP condition
mba607
P
PCA9665
© NXP B.V. 2006. All rights reserved.
2
C-bus controller
mba608
SDA
SCL
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