pca9665 NXP Semiconductors, pca9665 Datasheet - Page 71

• Manufacturer Part Number: pca9665
• Description: Fm+ Parallel Bus To I2c-bus Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
13. Dynamic characteristics
Table 49.
V
[1]
[2]
[3]
[4]
[5]
[6]
PCA9665_2
Product data sheet
Symbol
Initialization timing
t
Serial interface initialization timing
t
RESET timing (see
t
t
t
INT timing (see
t
t
Bus timing (see
t
t
t
t
t
t
t
t
t
t
t
t
init(po)
init(sintf)
w(rst)
rst
rec(rst)
as(int)
das(int)
su(A)
h(A)
su(CE_N)
h(CE_N)
w(RDL)
w(WRL)
d(DV)
d(QZ)
su(Q)
h(Q)
w(RDH)
w(WRH)
CC
= 3.3 V
Parameters are valid over specified temperature and voltage range.
All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of
5 ns maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in
Test conditions for outputs: C
Test conditions for open-drain outputs: C
Initialization time for the serial interface after ENSIO bit goes HIGH in a write operation to the control register.
Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.
Upon reset, the full delay will be the sum of t
Parameter
power-on initialization time
serial interface initialization time
reset pulse width
reset time
reset recovery time
interrupt assert time
interrupt de-assert time
address setup time
address hold time
CE setup time
CE hold time
RD LOW pulse width
WR LOW pulse width
data valid delay time
data output float delay time
data output setup time
data output hold time
RD HIGH pulse width
WR HIGH pulse width
Dynamic characteristics (3.3 volt)
0.3 V; T
Figure
Figure 38
Figure
amb
37)
= 40 C to +85 C; unless otherwise specified. (See
36)
and
L
= 50 pF; R
Figure
L
40)
L
= 50 pF; R
= 500 , except open-drain outputs.
[4]
rst
and the RC time constant of the SDA and SCL bus.
[1][2][3]
Rev. 02 — 7 December 2006
Conditions
from ENSIO bit HIGH
to RD, WR LOW
from RD, WR LOW
to RD, WR LOW
from RD, WR LOW
after RD and CE LOW
after RD or CE HIGH
before WR or CE HIGH (write cycle)
after WR HIGH
L
= 1 k pull-up to V
DD
.
Table 50 on page 72
Fm+ parallel bus to I
[5][6]
Min
-
-
10
250
0
-
-
0
13
0
0
20
20
-
-
12
0
18
18
for 2.5 V)
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Figure 38
PCA9665
© NXP B.V. 2006. All rights reserved.
2
C-bus controller
Max
550
550
-
-
-
500
20
-
-
-
-
-
-
17
17
-
-
-
-
and
Figure
71 of 91
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
40.