tda9850t-v1 NXP Semiconductors, tda9850t-v1 Datasheet - Page 13

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tda9850t-v1

Manufacturer Part Number
tda9850t-v1
Description
I2c-bus Controlled Btsc Stereo/sap Decoder
Manufacturer
NXP Semiconductors
Datasheet
Philips Semiconductors
1995 Jun 19
SAP output
Z
V
R
C
V
Outputs OUTL and OUTR
V
HEAD
Z
V
R
C
Dbx noise reduction circuit
t
I
I
I
Rel
adj
s
s range
t
SYMBOL
o
o
V
I
O
o(rms)
o(rms)
O
ct
L
L
L
L
I
s
2
ST-SAP
rate
C-bus controlled BTSC stereo/SAP decoder
o
output impedance
DC output voltage
output load resistance
(AC-coupled)
output load capacitance
nominal output voltage
(RMS value)
nominal output voltage
(RMS value)
output headroom
output impedance
DC output voltage
output load resistance
(AC-coupled)
output load capacitance
crosstalk L, R into SAP
crosstalk SAP into L, R
output voltage difference
if switched from L, R to
SAP
stereo adjustment time
nominal timing current for
nominal release rate of
spectral RMS detector
spread of timing current
timing current range
timing current for release
rate of wideband RMS
detector
nominal RMS detector
release rate
wideband
spectral
PARAMETER
150 s de-emphasis
100% modulation
100% modulation;
f
mode selector switched
to SAP/SAP
100% modulation;
f
mode selector switched
to stereo
250 Hz to 6.3 kHz
see Section “Adjustment
procedure”
I
C
connected to
1
7 steps via I
nominal timing current
and external capacitor
values
i
i
s
2
= 1 kHz; L or R;
= 1 kHz; SAP;
TS
can be measured at pin
V
CC
via current meter
CONDITIONS
+ 0.25 V
2
C-bus
13
5
9
0.45V
5
50
50
15
MIN.
CC
1.5 0.5V
80
0.5V
500
80
75
70
24
1
125
381
30
3
I
s
TYP.
CC
CC
see Fig.3
1.5
1.5 0.55V
Preliminary specification
120
2.5
120
2.5
3
1
+15
MAX.
TDA9850
CC
1.5 V
V
k
nF
mV
dB
k
nF
dB
dB
dB
s
%
%
dB/s
dB/s
UNIT
A
A

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