tda9850t-v1 NXP Semiconductors, tda9850t-v1 Datasheet - Page 16

• Manufacturer Part Number: tda9850t-v1
• Description: I2c-bus Controlled Btsc Stereo/sap Decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
I
Table 4 Explanation of I
If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress
and auto-increment of subaddress in accordance with the order of Table 5 is performed.
Table 5 Subaddress second byte after MAD
Table 6 Definition of third byte, third byte after MAD and SAD
1995 Jun 19
2
S
Standard SLAVE ADDRESS (MAD)
Pin programmable SLAVE ADDRESS
R/W
A
SUBADDRESS (SAD)
DATA
P
Control 1
Control 2
Control 3
Control 4
Alignment 1
Alignment 2
Alignment 3
Control 1
Control 2
Control 3
Control 4
Alignment 1
Alignment 2
Alignment 3
C-bus format to write (slave receives data)
I
2
S
C-bus controlled BTSC stereo/SAP decoder
FUNCTION
FUNCTION
SLAVE ADDRESS
NAME
2
CON1
CON2
CON3
CON4
ALI1
ALI2
ALI3
CON1
CON2
CON3
CON4
ALI1
ALI2
ALI3
C-bus format to write (slave receives data)
REGISTER
REGISTER
R/W
MSB
MSB
SAP
STS
ADJ
D7
D7
0
0
0
0
0
0
0
0
0
0
0
A
STEREO
START condition
101 101 1 pin MAD not connected
101 101 0 pin MAD connected to ground
0 (write)
acknowledge; generated by the slave
see Table 5
see Table 6
STOP condition
D6
D6
0
0
0
0
0
0
0
0
0
0
0
0
0
SUBADDRESS
16
D5
D5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SMU
A14
A24
D4
D4
0
0
0
0
0
0
0
0
0
0
0
DESCRIPTION
A
LMU
ST3
SP3
A13
A23
D3
D3
L3
0
0
0
0
1
1
1
0
DATA
SP2
TC2
ST2
A12
A22
D2
D2
L2
Preliminary specification
1
1
1
1
0
0
0
0
TDA9850
ST1
SP1
TC1
A21
A11
D1
D1
L1
0
0
1
1
0
0
1
0
A
LSB
LSB
ST0
SP0
TC0
A10
A20
D0
D0
L0
0
1
0
1
0
1
0
0
P