dac1205d650 NXP Semiconductors, dac1205d650 Datasheet - Page 22

• Manufacturer Part Number: dac1205d650
• Description: Dual 12-bit Dac, Up To 650 Msps; 2? 4? And 8? Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1205D650_1
Product data sheet
In the Interleaved mode, both DACs use the same data input at twice the Dual-port mode
frequency. Data enters the latch on the rising edge of the internal clock signal. The data is
sent to either latch I or latch Q, depending on the SELIQ signal; see
The SELIQ input (pin 41) allows the synchronization of the internally de-multiplexed I and
Q channels; see
edge)”.
SELIQ can be either a synchronous or asynchronous (single rising edge, single pulse)
signal. The first data bits following the SELIQ rising edge are sent in channel I and
following data bits are sent in channel Q. After this, the data is distributed alternately
between both channels.
Fig 6.
Fig 7.
(asynchronous alternative 1)
(asynchronous alternative 2)
n in Qn = 11 and for In is 0 to 11.
Interleaved mode operation
Interleaved mode timing (8 interpolation, latch on rising edge)
(synchronous alternative)
Qn/SELIQ
In
Figure 7 “Interleaved mode timing (8¥ interpolation, latch on rising
Latch Q output
Latch I output
CLK
SELIQ
SELIQ
SELIQ
Rev. 01 — 28 July 2009
Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
dig
In
LATCH
LATCH
Q
I
N
N + 1
2
2
XX
XX
FIR 1
FIR 1
N + 2
2
2
FIR 2
FIR 2
N + 3
N + 1
N
DAC1205D650
N + 4
Figure
2
2
FIR 3
FIR 3
© NXP B.V. 2009. All rights reserved.
N + 5
N + 2
N + 3
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7.
001aaj814
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