dac1205d650 NXP Semiconductors, dac1205d650 Datasheet - Page 30

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dac1205d650

Manufacturer Part Number
dac1205d650
Description
Dual 12-bit Dac, Up To 650 Msps; 2? 4? And 8? Interpolating
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
DAC1205D650_1
Product data sheet
10.12 Analog output
Table 38.
Default settings are shown highlighted.
The DAC1205D650 has two output channels each of which produces two complementary
current outputs. These allow the even-order harmonics and noise to be reduced. The pins
are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected using
a load resistor R
Refer to
output circuit of one DAC. This circuit consists of a parallel combination of NMOS current
sources, and their associated switches, for each segment.
The cascode source configuration increases the output impedance of the source, thus
improving the dynamic performance of the DAC by introducing less distortion.
The device can provide an output level of up to 2 V
following stages and the targeted performances.
DAC_OFFSET[10:0]
Decimal
...
0
+1
...
+1022
+1023
Fig 12. Equivalent analog output circuit (one DAC)
1024
1023
1
Figure 12 “Equivalent analog output circuit (one DAC)”
Digital offset adjustment
L
to the 3.3 V analog power supply (V
Rev. 01 — 28 July 2009
Dual 12-bit DAC, up to 650 Msps; 2 4 and 8 interpolating
AGND
Two’s complement
100 0000 0000
100 0000 0001
...
111 1111 1111
000 0000 0000
000 0000 0001
...
011 1111 1110
011 1111 1111
AGND
IOUTAP/IOUTBP
IOUTAN/IOUTBN
o(p-p)
DDA(3V3)
depending on the application, the
DAC1205D650
Offset applied
...
0
+1
...
+1022
+1023
V
1024
1023
1
).
DDA(3V3)
R L
001aah019
for the equivalent analog
R L
© NXP B.V. 2009. All rights reserved.
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