dsp56367 Freescale Semiconductor, Inc, dsp56367 Datasheet - Page 29
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dsp56367
Manufacturer Part Number
dsp56367
Description
Dsp56367 24-bit Audio Digital Signal Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56367.pdf
(100 pages)
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3.7
The DSP56367 system clock is an externally supplied square wave voltage source connected to
EXTAL(Figure
Freescale Semiconductor
1
2
Internal clock cycle time with PLL disabled
Instruction cycle time
No.
DF = Division Factor
Ef = External frequency
ET
MF = Multiplication Factor
PDF = Predivision Factor
T
Refer to the
1
2
3
C
C
= internal clock cycle
= External clock cycle
Frequency of EXTAL (EXTAL Pin Frequency)
The rise and fall time of this external clock should be 2 ns maximum.
EXTAL input high
EXTAL input low
• With PLL disabled (46.7%–53.3% duty cycle
• With PLL enabled (42.5%–57.5% duty cycle
• With PLL disabled (46.7%–53.3% duty cycle
• With PLL enabled (42.5%–57.5% duty cycle
External Clock Operation
DSP56300 Family Manual
Characteristics
Note: The midpoint is 0.5 (V
3-1).
EXTAL
1, 2
1, 2
V
ILC
Characteristics
ET
for a detailed discussion of the PLL.
Table 3-4 Internal Clocks (continued)
H
Figure 3-1 External Clock Timing
DSP56367 Technical Data, Rev. 2.1
2
Table 3-5 Clock Operation
IHC
Symbol
+ V
I
4
CYC
T
ILC
C
ET
3
3
3
3
)
)
)
)
).
L
3
ET
C
Min
—
—
Symbol
ET
ET
Expression
Ef
H
Midpoint
L
2 × ET
Typ
T
C
C
1, 2
3.11 ns
2.83 ns
3.11 ns
2.83 ns
2.0 ns
External Clock Operation
Min
V
IHC
Max
157.0 µs
157.0 µs
—
—
150.0
Max
∞
∞
3-5
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