dsp56004 Freescale Semiconductor, Inc, dsp56004 Datasheet - Page 30

• Manufacturer Part Number: dsp56004
• Description: Symphonytm Audio Dsp Family 24-bit Digital Signal Processors
• Manufacturer: Freescale Semiconductor, Inc

Specifications
Phase Lock Loop (PLL) Characteristics
PHASE LOCK LOOP (PLL) CHARACTERISTICS
2-6
Note:
No.
3 External Clock Cycle Time
4 Instruction Cycle Time = I
VCO frequency when PLL enabled
PLL external capacitor
(PCAP pin to V
Note:
• with PLL disabled
• with PLL enabled
• with PLL disabled
• with PLL enabled
EXTAL
1.
1.
External Clock Input High and External Clock Input Low are measured at 50% of the input transition.
Cpcap is the value of the PLL capacitor (connected between PCAP pin and V
The recommended value for Cpcap is 400 pF for MF 4 and 540 pF for MF > 4.
The maximum VCO frequency is limited to the internal operation frequency, defined in Table 2-4.
Characteristics
CCP
Characteristics
)
Table 2-5 External Clock (EXTAL Pin) (Continued)
Table 2-6 Phase Lock Loop (PLL) Characteristics
ET
1
cyc
Freescale Semiconductor, Inc.
1
H
For More Information On This Product,
= 2
Figure 2-1 External Clock Timing
ET
3
T
DSP56004/D, Rev. 3
C
C
1
Go to: www.freescale.com
ET
2
Sym.
I
ET
L
CYC
MF
Expression
C
MF
Min
@ MF 4
@ MF > 4
C
20
20
40
40
4
PCAP
50 MHz
Ef
409600
819200
1
Max
15.15
15.15 409600
MF
MF
Min
30.3
30.3 819200
Min
66 MHz
10
340
380
Max
MF
MF
CCP
Min
Max
12.3
12.3 409600
24.7
24.7 819200
f
) for MF = 1.
81 MHz
1
480
970
MOTOROLA
Max
MHz
AA0250
Unit
pF
pF
Unit
ns
ns
ns
ns