dsp56004 Freescale Semiconductor, Inc, dsp56004 Datasheet - Page 9

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dsp56004

Manufacturer Part Number
dsp56004
Description
Symphonytm Audio Dsp Family 24-bit Digital Signal Processors
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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POWER
GROUND
MOTOROLA
V
V
V
V
V
GND
GND
GND
GND
GND
CCP
CCQ
CCA
CCD
CCS
Ground Name
Power Name
P
Q
A
D
S
PLL Ground—GND
provided with an extremely low-impedance path to ground. V
bypassed to GND
package.
Quiet Ground—GND
This connection must be tied externally to all other chip ground connections. The
user must provide adequate external decoupling capacitors.
Address Bus Ground—GND
bus I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Data Bus Ground—GND
drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Serial Interface Ground—GND
connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
PLL Power—V
voltage should be well-regulated and the input should be provided with an
extremely low impedance path to the V
Quiet Power—V
input must be tied externally to all other chip power inputs. The user must provide
adequate external decoupling capacitors.
Address Bus Power—V
I/O drivers. This input must be tied externally to all other chip power inputs. The
user must provide adequate external decoupling capacitors.
Data Bus Power—V
drivers. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors.
Serial Interface Power—V
input must be tied externally to all other chip power inputs. The user must provide
adequate external decoupling capacitors.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
CCP
CCQ
P
Table 1-2 Power Inputs
DSP56004/D, Rev. 3
provides isolated power for the Phase Lock Loop (PLL). The
by a 0.47 F capacitor located as close as possible to the chip
CCD
P
Table 1-3 Grounds
provides isolated power for the internal processing logic. This
is ground dedicated for PLL use. The connection should be
Q
CCA
provides isolated ground for the internal processing logic.
provides isolated power for sections of the data bus I/O
D
CCS
provides isolated ground for sections of the data bus I/O
provides isolated power for sections of the address bus
A
provides isolated power for the SHI and SAI. This
provides isolated ground for sections of the address
S
provides isolated ground for the SHI and SAI. This
Description
Description
CC
power rail.
Signal/Connection Descriptions
CCP
should be
Power
1-3

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