saa7130hl-v1 NXP Semiconductors, saa7130hl-v1 Datasheet - Page 38

• Manufacturer Part Number: saa7130hl-v1
• Description: Pci Video Broadcast Decoder
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 20:
[1]
10. Test information
SAA7130HL_4
Product data sheet
Standard
External components
Typical load capacitance
at pin XTALI
Typical load capacitance
at pin XTALO
Typical capacitance of
LC filter
Typical inductance of
LC filter
For oscillator application, see the Application note of the SAA7130HL/34HL .
Specification of crystals and related applications (examples)
10.1.1 Initialization of boundary scan circuit
10.1.2 Device identification codes
10.1 Boundary scan test
The SAA7130HL has built-in logic and five dedicated pins to support boundary scan
testing which allows board testing without special hardware (nails).
The SAA7130HL follows the IEEE Std. 1149.1 - Standard Test Access Port and Boundary
- Scan Architecture set by the Joint Test Action Group (JTAG) chaired by Philips.
The 5 special pins are: Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST_N),
Test Data Input (TDI) and Test Data Output (TDO).
The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and
IDCODE are all supported (see
in the specification IEEE Std. 1149.1 . A file containing the detailed Boundary Scan
Description Language (BSDL) description of the SAA7130HL is available on request.
The Test Access Port (TAP) controller of an IC should be in the reset state
(TEST_LOGIC_RESET) when the IC is in the functional mode. This reset state also
forces the instruction register into a functional instruction such as IDCODE or BYPASS.
To solve the power-up reset, the standard specifies that the TAP controller will be forced
asynchronously to the TEST_LOGIC_RESET state by setting pin TRST_N to LOW-level.
When the IDCODE instruction is loaded into the BST instruction register, the identification
register will be connected internally between pins TDI and TDO of the IC. The
identification register will load a component specific code during the
CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently
be shifted out. At board level, this code can be used to verify component manufacturer,
Crystal frequency
32.11 MHz
Fundamental
1B
33
33
n.a.
n.a.
1C
10
10
n.a.
n.a.
Rev. 04 — 11 April 2006
3rd harmonic
1A
15
15
1
4.7
Table
21). Details about the JTAG BST-test can be found
24.576 MHz
Fundamental
2B
27
27
n.a.
n.a.
[1]
…continued
2C
5.6
5.6
n.a.
n.a.
PCI video broadcast decoder
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
SAA7130HL
3rd harmonic
2A
18
18
1
4.7
38 of 46
pF
pF
nF
Unit
H