ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 269
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ep2sgx30c
Manufacturer Part Number
ep2sgx30c
Description
Stratix Ii Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP2SGX30C.pdf
(314 pages)
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Altera Corporation
October 2007
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class I I
1.5-V HSTL Class I
1.5-V HSTL Class I I
1.8-V HSTL Class I
1.8-V HSTL Class II
Differential SSTL-2
Class I
Differential SSTL-2
Class II
Differential SSTL-18
Class I
PCI
PCI-X
Table 4–88. Stratix II GX Maximum Input Clock Rate for Column I/O Pins (Part 1 of 2)
I/O Standard
-3 Speed Grade
To calculate the output toggle rate for a non 0 pF load, use this formula:
The toggle rate for a non 0 pF load
For example, the output toggle rate at 0 pF load for SSTL-18 Class II
20 mA I/O standard is 550 MHz on a -3 device clock output pin. The
derating factor is 94 ps/pF. For a 10 pF load the toggle rate is calculated
as:
Table 4–88
device column pins.
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
= 1,000 / (1,000/ toggle rate at 0 pF load + derating factor × load
value in pF /1,000)
1,000 / (1,000/550 + 94 × 10 /1,000) = 363 (MHz)
shows the maximum input clock toggle rates for Stratix II GX
-4 Speed Grade
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
Stratix II GX Device Handbook, Volume 1
-5 Speed Grade
DC and Switching Characteristics
450
450
450
450
450
500
500
500
500
500
500
500
500
450
450
500
500
500
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
4–99
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