ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 301

• Manufacturer Part Number: ep2sgx30c
• Description: Stratix Ii Gx Device Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
October 2007
Notes to
(1)
(2)
f
% spread
t
t
t
t
f
f
f
t
f
f
SS
P L L _ P S E R R
ARESET
ARESET_RECONFIG
RECONFIGWAIT
IN
INPFD
INDUTY
INJITTER
VCO
OUT
Table 4–110. Enhanced PLL Specifications (Part 2 of 2)
Table 4–111. Fast PLL Specifications (Part 1 of 2)
This is limited by the I/O f
If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
Name
Name
Table
4–110:
Input clock frequency (for -3 and -4 speed
grade devices)
Input clock frequency (for -5 speed grade
devices)
Input frequency to the PFD
Input clock duty cycle
Input clock jitter tolerance in terms of period
jitter. Bandwidth
Input clock jitter tolerance in terms of period
jitter. Bandwidth > 0.2 MHz
Upper VCO frequency range for –3 and –4
speed grades
Upper VCO frequency range for –5 speed
grades
Lower VCO frequency range for –3 and –4
speed grades
Lower VCO frequency range for –5 speed
grades
PLL output frequency to
PLL output frequency to LVDS or DPA clock
Spread-spectrum modulation frequency
Percent down spread for a given clock
frequency
Accuracy of PLL phase shift
Minimum pulse width on
Minimum pulse width on the
signal when using PLL reconfiguration.
Reset the PLL after
The time required for the wait after the
reconfiguration is done and the areset is
applied.
MAX
. See
Description
Description
Tables 4–91
≤
2 MHz
scandone
GCLK
areset
through
areset
or
goes high.
RCLK
signal.
4–95
for the maximum.
4.6875
Stratix II GX Device Handbook, Volume 1
Min
100
500
0.4
Min
300
300
150
150
150
10
16
16
16
40
DC and Switching Characteristics
Typ
0.5
Typ
0.5
1.0
Max
1,040
1,040
500
±30
0.6
Max
717
640
500
840
520
420
550
2
60
ns (p-p)
ns (p-p)
Unit
kHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ps
ns
ns
us
%
4–131
%