ep2sgx30c Altera Corporation, ep2sgx30c Datasheet - Page 272

• Manufacturer Part Number: ep2sgx30c
• Description: Stratix Ii Gx Device Data Sheet
• Manufacturer: Altera Corporation

Timing Model
4–102
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
(2)
Class I
Class II
Class I
Class II
HSTL Class I
HSTL Class II
HSTL Class I
HSTL Class I I
Differential SSTL-18
Differential SSTL-18
1.8-V HSTL CLass I
PCI
PCI-X
Differential SSTL-2
Differential SSTL-2
1.8-V differential
1.8-V differential
1.5-V differential
1.5-V differential
HyperTransport
LVPECL (1),
LVDS
Table 4–90. Stratix II GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 2 of 2)
I/O Standard
The first set of numbers refers to the HIO dedicated clock pins. The second set of numbers refers to the VIO
dedicated clock pins.
LVPECL is only supported on column clock pins.
(1)
Table
(2)
4–90:
(1)
-3 Speed Grade
500
500
500
500
500
500
500
500
500
500
500
717
450
717
450
717
450
-4 Speed Grade
500
500
500
500
500
500
500
500
500
500
500
717
450
717
450
717
450
-5 Speed Grade
500
400
400
500
500
500
500
500
500
500
500
640
400
640
400
640
400
Altera Corporation
October 2007
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz