ade7753 Analog Devices, Inc., ade7753 Datasheet - Page 12

• Manufacturer Part Number: ade7753
• Description: Active And Apparent Energy Metering Ic With Di/dt Sensor Interface
• Manufacturer: Analog Devices, Inc.

ADE7753
POWER SUPPLY MONITOR
The ADE7753 also contains an on-chip power supply moni-
tor. The Analog Supply (AV
by the ADE7753. If the supply is less than 4V ± 5% then the
ADE7753 will go into an inactive state, i.e. no energy will be
accumulated when the supply voltage is below 4V. This is
useful to ensure correct device operation at power up and
during power down. The power supply monitor has built-in
hysteresis and filtering. This gives a high degree of immunity
to false triggering due to noisy supplies.
As can be seen from Figure 12 the trigger level is nominally
set at 4V. The tolerance on this trigger level is about ±5%.
The SAG pin can also be used as a power supply monitor
input to the MCU. The SAG pin will go logic low when the
ADE7753 is in its inactive state. The power supply and
decoupling for the part should be such that the ripple at
AV
operation.
LINE VOLTAGE SAG DETECTION
In addition to the detection of the loss of the line voltage
signal (zero crossing), the ADE7753 can also be pro-
grammed to detect when the absolute value of the line voltage
drops below a certain peak value, for a number of line cycles.
This condition is illustrated in Figure 13 below.
Figure 13 shows the line voltage fall below a threshold which
is set in the Sag Level register (SAGLVL[7:0]) for five line
cycles. Since the Sag Cycle register (SAGCYC[7:0]) con-
SAGLVL[7:0]
DD
Full Scale
Power-on
SAG
ADE7753
does not exceed 5V±5% as specified for normal
Inactive
AV DD
Figure 12 - On-Chip power supply monitor
SAG
State
5V
4V
0V
Figure 13– ADE7753 Sag detection
Inactive
SAGCYC[7:0] = 06H
6 half cycles
Channel 2
Active
Time
PRELIMINARY TECHNICAL DATA
DD
) is continuously monitored
Inactive
SAG reset high
when Channel 2
exceeds SAGLVL[7:0]
–12–
tains 03h the SAG pin will go active low at the end of the fifth
line cycle for which the line voltage falls below the threshold,
if the DISSAG bit in the Mode register is logic zero. As is
the case when zero-crossings are no longer detected, the sag
event is also recorded by setting the SAG flag in the Interrupt
Status register. If the SAG enable bit is set to logic one, the
IRQ logic output will go active low - see ADE7753 Interrupts.
The SAG pin will go logic high again when the absolute value
of the signal on Channel 2 exceeds the sag level set in the Sag
Level register. This is shown in Figure 13 when the SAG pin
goes high during the tenth line cycle from the time when the
signal on Channel 2 first dropped below the threshold level.
Sag Level Set
The contents of the Sag Level register (1 byte) are compared
to the absolute value of the most significant byte output from
LPF1, after it is shifted left by one bit. Thus for example the
nominal maximum code from LPF1 with a full scale signal
on Channel 2 is 2518h—see Channel 2 sampling. Shifting one
bit left will give 4A30h. Therefore writing 4Ah to the SAG
Level register will put the sag detection level at full scale.
Writing 00h will put the sag detection level at zero. The Sag
Level register is compared to the most significant byte of a
waveform sample after the shift left and detection is made
when the contents of the sag level register are greater.
PEAK DETECTION
The ADE7753 can also be programmed to detect when the
absolute value of the voltage or the current channel of one
phase exceeds a certain peak value. Figure 14 illustrates the
behavior of the peak detection for the voltage channel.
Both channel 1 and channel 2 are monitored at the same time.
Figure 14 shows a line voltage exceeding a threshold which
is set in the Voltage peak register (VPKLVL[7:0]). The
Voltage Peak event is recorded by setting the PKV flag in the
Interrupt Status register. If the PKV enable bit is set to logic
one in the Interrupt Mask register, the IRQ logic output will
go active low. Similarly, the Current Peak event is recorded
by setting the PKI flag in the Ineterrupt Status register—see
ADE7753 Interrupts.
Peak Level Set
The contents of the VPKLVL and IPKLVL registers are
respectively compared to the absolute value of channel 1 and
channel 2, after they are multiplied by 2.
Read RSTSTATUS register
(Bit 8 of STATUS register)
PKV Interrupt Flag
VPKLVL[7:0]
Figure 14 - ADE7753 Peak detection
V 2
REV. PrF 10/02
PKV reset low
when RSTSTATUS register
is read