ade7753 Analog Devices, Inc., ade7753 Datasheet - Page 37

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ade7753

Manufacturer Part Number
ade7753
Description
Active And Apparent Energy Metering Ic With Di/dt Sensor Interface
Manufacturer
Analog Devices, Inc.
Datasheet

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REVISION HISTORY
The main reason for revising the datasheet from version Pr.D
to Pr.F is to correct some of the mistakes contained in the
Pr.D and Pr.E version. In addition, changes were made to the
silicon to fix bugs noted in the Errata list and to modify the
product definition.
changes from Pr.D to Pr.F. Note that all page numbers are
referring to that of Pr.F.
Page 4
Read timing t
Page 12
The SAGCYC register value represents full-line cycles and
not half-line cycles. The line voltage SAG detection section
text was changed to reflect this design update.
shows 3 line cycles, 3h in the SAGCYC register, changed
from 6 half line cycles, 6h in the SAGCYC register. The
section explaining Figure 13 has also changed accordingly.
Page 13
Peak Level record section was changed to show that the
quantity stored in VPEAK register is 2 times the absolute
value of the WAVEFORM register contents for CH2. IPEAK
is 1 times the absolute value of the CH1 Waveform.
Page 18
1. The phase calibration register resolution has changed to
0.048 from 0.024.
changed to reflect this new resolution.
2. Figure 27 updated with new PHCAL range and delay
block rate.
Page 20
Figure 36 Timing was updated.
Page 21
1. The internal active energy accumulation register is 47 bits
instead of 53 bits. The equation also shows this change. This
change is also implemented in the equations of page 25 as
well as Figures 45 and 47 on page 25.
2. The maximum output frequency is changed to 23Hz.
3. Text added to explain CFNUM must be less than
C F D E N .
Page 22
1. Figure 39 shows the actual internal register length to be 47
bits. This change is also on page 23, Figure 41.
2. Line Cycle Energy accumulation mode section changed to
15 bits for LINECYC Register.
REV. PrF 10/02
9
is determined to be 3.1us.
The list below highlights the important
This section calculations have been
PRELIMINARY TECHNICAL DATA
Figure 13
–37–
Page 26
1. Equation 25 changed to have 2^27 bits for the denomina-
tor.
2. Content of LAENERGY register is 2971.4, and the CF
frequency output in the example calculation is 1398.3 Hz.
3. The calculation of CFNUM and CFDEN changed
according to the effect of the abovementioned changes.
Page 31
1. The definition of the SAGCYC a register has changed to
full line cycles.
remains half line cycles.
2. The PHCAL register description changed to reflect the
new effective length and resolution of the register and default
value of 0D.
LINECYC corrected to say 15 bits and
ADE7753

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