ade7753 Analog Devices, Inc., ade7753 Datasheet - Page 31

• Manufacturer Part Number: ade7753
• Description: Active And Apparent Energy Metering Ic With Di/dt Sensor Interface
• Manufacturer: Analog Devices, Inc.

Address Name
REV. PrF 10/02
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1C h
1D h
1Eh
1F h
20h
PHCAL
APOS
WG AIN
WD IV
C F N U M
C F D E N
IRMS
VRMS
I R M S O S
VRMSOS
VAGAIN
VADIV
L I N E C Y C
Z X T O U T
SAGCYC
SAGLVL
IPKLVL
R/W
R/W 6 bits
R/W 16 bits
R/W 12 bits
R/W 8 bits
R/W 12 bits
R/W 12 bits
R
R
R/W 12 bits
R/W 12 bits
R/W 12 bits
R/W 8 bits
R/W 15 bits
R/W 12 bits
R/W 8 bits
R/W 8 bits
R/W 8 bits
PRELIMINARY TECHNICAL DATA
# of Bits
24 bits
24 bits
Default
F F F h
F F h
0h
F F h
0D h
0h
0h
0h
3F h
3F h
0h
0h
0h
0h
0h
0h
F F F h
Description
Phase Calibration register. The phase relationship between
Channel 1 and 2 can be adjusted by writing to this 6-bit register.
The valid content of this 2's compliment register is between 1Dh
to 21h. At line frequency of 60Hz, this is a range from -2.06 to
+0.7 degrees. —see Phase Compensation.
Active Power Offset Correction. This 16-bit register allows small
offsets in the Active Power Calculation to be removed – see
Active Power Calculation.
Power Gain Adjust. This is a 12-bit register. The Active Power
calculation can be calibrated by writing to this register. The
calibration range is ±50% of the nominal full scale active power.
The resolution of the gain adjust is 0.0244% / LSB—see Channel
1 ADC Gain Adjust.
Active Energy divider register. The internal active energy register
is divided by the value of this register before being stored in the
AENERGY register.
CF Frequency Divider Numerator register. The output frequency
on the CF pin is adjusted by writing to this 12-bit read/write
register – see Energy to Frequency Conversion.
CF Frequency Divider Denominator register. The output
frequency on the CF pin is adjusted by writing to this 12-bit
read/write register – see Energy to Frequency Conversion.
Channel 1 RMS value (current channel).
Channel 2 RMS value (voltage channel).
Channel 1 RMS offset correction register
Channel 2 RMS offset correction register
Apparent Gain register. Apparent power calculation can be
calibrated by writing this register. The calibration range is 50%
of the nominal full scale real power. The resolution of the gain
adjust is 0.02444% / LSB.
Apparent Energy divider register. The internal apparent energy
register is divided by the value of this register before being stored
in the VAENERGY register.
Line Cycle Energy Accumulation Mode Line-Cycle register.
This 15-bit register is used during line cycle energy
accumulation mode to set the number of half line cycles for
energy accumulation - see Line Cycle Energy Accumulation Mode.
Zero-cross Time Out. If no zero crossings are detected on
Channel 2 within a time period specified by this 12-bit register,
the interrupt request line (IRQ) will be activated. The maximum
time-out period is 0.15 second - see Zero Crossing Detection.
Sag line Cycle register. This 8-bit register specifies the number
of consecutive line cycles the signal on Channel 2 must be below
SAGLVL before the SAG output is activated - see Voltage Sag
Detection
Sag Voltage Level. An 8-bit write to this register determines at
what peak signal level on Channel 2 the SAG pin will become
active. The signal must remain low for the number of cycles
specified in the SAGCYC register before the SAG pin is
activated—see Line Voltage Sag Detection.
Channel 1 Peak Level threshold (current channel). This register
sets the level of the current peak detection. If the channel 1 input
exceeds this level, the PKI flag in the status register is set.
–31–
ADE7753