ml670100 Oki Semiconductor, ml670100 Datasheet - Page 184

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

11.3.3.2 Basic Access
11.3.3.3 Access with Wait Cycles
11.3.3.3.1 RAS Precharge Time
11-28
SYSCLK
(CLKOUT)
XA15 - XA0
nRAS
nCAS
XD15 - XD0
Basic access, access without wait cycles, to a DRAM bank (2 or 3) takes two clock cycles for a
read or a write.
Figure 11.21 shows the basic access timing for external memory areas in these two banks.
The RAS Precharge (RP) bit in the DRAM Bank 2 and 3 Access Timing Control Registers
(ATnCON, n=2,3) adjusts the t
match the system clock (SYSCLK) frequency and the type of DRAM used.
Figure 11.22 gives the timings for both selections.
SYSCLK
(CLKOUT)
XA15 - XA0
nRAS
nCAS
XD15 - XD0
nWE
Figure 11.21 :Basic External Access Timing for DRAM Banks (2 and 3)
Row
Read cycle
Figure 11.22 : RAS Precharge Timing
Col
Row
Read cycle
RP
, the RAS precharge time, for bank n to 1 or 2 clock cycles to
Col
Row
Read cycle
One cycle
Col
Row
Write cycle
Col
Row
Read cycle
Two cycles
Col