ml670100 Oki Semiconductor, ml670100 Datasheet - Page 53
ml670100
Manufacturer Part Number
ml670100
Description
Ml670100 Is A High-performance 32-bit Microcontroller
Manufacturer
Oki Semiconductor
Datasheet
1.ML670100.pdf
(204 pages)
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4.2
4.2.1
4.2.2
There are three types of interrupt requests: external fast interrupt requests producing FIQ
exception requests, external interrupt requests producing IRQ exception requests, and internal
interrupt requests producing IRQ exception requests.
An external fast interrupt request sends the CPU an FIQ exception request unless blocked with
the external FIQ mask (EFIQM) flag.
The other two types only send the CPU an IRQ exception request if the interrupt level specified
for the corresponding source is higher than the highest level flagged in the Current Interrupt
Level Register (CILR), which holds interrupt level flags for the interrupts currently being
processed. If the source's interrupt level is the same or lower than the highest level flagged in
CILR, however, the interrupt request is held pending and only sends the CPU an IRQ exception
request when the latter drops below the former.
If the interrupt controller detects a falling edge in the input signal from the external fast
interrupt request (nEFIQ) pin and the external FIQ mask (EFIQM) flag in the External FIQ
Control Register (EFIQCON) is "0" - that is, masking is off - it sends the CPU an FIQ
exception request. The CPU only accepts this exception request if the F bit in its Current
Program Status Register (CPSR) is "0."
If the interrupt controller detects the input (a falling edge or "L" level) specified with the EIRn
(n=0 - 7) bit in the External IRQ Control Register (EIRCON) from External Interrupt Request
n pin (nEIR[n], n=0 - 7) and the interrupt level specified for the corresponding source is higher
than the highest level flagged in the Current Interrupt Level Register (CILR), which holds
interrupt level flags for the interrupts currently being processed, it sends the CPU an IRQ
exception request. The CPU only accepts this exception request if the I bit in its Current
Program Status Register (CPSR) is "0."
Interrupt Sources
External Fast Interrupt Requests
External Interrupt Requests
4-5
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