ml670100 Oki Semiconductor, ml670100 Datasheet - Page 69

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ml670100

Manufacturer Part Number
ml670100
Description
Ml670100 Is A High-performance 32-bit Microcontroller
Manufacturer
Oki Semiconductor
Datasheet
4.6
SYSCLK(CLKOUT)
nEIR[n]
(n=0-7) pin
A bit in IRR3
SYSCLK(CLKOUT)
nEIR[n]
(n=0-7) pin
A bit in IRR3
Table 4.4 indicates the number of clock cycles between the arrival of an interrupt and the start
of the fetch cycle for the instruction at the vector address.
Note that even if an interrupt has set the corresponding interrupt request flag, there are two
cases when it does not produce an immediate FIQ or IRQ exception.
- The interrupt controller is masking the interrupt.
- The interrupt has a level less than or equal to that of the interrupt currently being processed.
The interrupt controller does not generate an interrupt request to the CPU until both conditions
no longer apply.
The CPU ignores such requests until both the F or I bit in the Current Program Status Register
(CPSR) is "0."
Interrupt Response Times
Figure 4.11 : Sampling Timing for External Interrupt Requests
(a) Using falling edge sensing for interrupt request detection
(b) Using "L" level sensing for interrupt request detection
Set
Set
4-21

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